# Publications

Last modified: 12/18/07.

Disclaimer: Papers are made available on this webpage to ensure
timely dissemination of research results. Copyright and all rights
therein are retained by authors or other copyright holders.
In particular, the papers that appeared in Design Automation
Conference are available here due to the
copyright policy of ACM.

## 2008

#### DAC

A. P. Hurst, A. Mishchenko, and R. K. Brayton,
"Scalable min-area retiming under simultaneous delay and
initial state constraints". Submitted to DAC'08.
PDF
M. L. Case, V. N. Kravets, A. Mishchenko, and R. K. Brayton,
"Merging nodes under sequential observability", Submitted to DAC'08.
PDF
A. Mishchenko, M. Case, R. Brayton, and S. Jang,
"Scalable and scalably-verifiable sequential synthesis",
Submitted to DAC'08. PDF
A. Mishchenko and R. Brayton,
"Recording synthesis history for sequential verification",
Submitted to DAC'08. PDF

## 2007

#### ICCAD

A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton,
"Combinational and sequential mapping with priority cuts",
Proc. ICCAD '07, pp. 354-361.
PDF
F. Mo and R. K. Brayton. "A simultaneous bus orientation
and bused pin flipping algorithm", Proc. ICCAD '07, pp. 386-389.
PDF
#### FMCAD

M. L. Case, A. Mishchenko, and R. K. Brayton,
"Automated extraction of inductive invariants to aid model checking",
Proc. FMCAD '07.
PDF
A. Hurst, A. Mishchenko, and R. Brayton,
"Fast minimum-register retiming via binary maximum-flow",
Proc. FMCAD '07.
PDF
#### ISPD

F. Mo and R. Brayton,
"Semi-detailed bus routing and variation reduction".
Proc. ISPD '07, pp. 143-150.
PDF
#### DAC

S. Chatterjee, A. Mishchenko, R. Brayton, and A. Kuehlmann,
"On resolution proofs for combinational equivalence".
Proc. DAC '07, pp. 600-605.
PDF
#### IWLS

R. Brayton and A. Mishchenko,
"Sequential rewriting",
Proc. IWLS '07, pp. 1-8.
PDF
A. Hurst, A. Mishchenko, and R. Brayton,
"Minimizing implementation costs with end-to-end retiming",
Proc. IWLS '07, pp. 9-16.
PDF
A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton,
"Combinational and sequential mapping with priority cuts",
Proc. IWLS '07, pp. 91-98. (See ICCAD'07.)
J. Pistorius, M. Hutton, A. Mishchenko, and R. Brayton.
"Benchmarking method and designs targeting logic synthesis for FPGAs",
Proc. IWLS '07, pp. 230-237.
PDF
M. L. Case, A. Mishchenko, and R. K. Brayton,
"Automated extraction of inductive invariants to aid model checking",
Proc. IWLS '07, pp. 282-289. (See FMCAD'07.)
A. Hurst, A. Mishchenko, and R. Brayton,
"Fast minimum-register retiming via binary maximum-flow",
Proc. IWLS '07, pp. 328-335. (See FMCAD'07.)
S. Chatterjee, Z. Wei, A. Mishchenko, and R. Brayton,
"A linear time algorithm for optimum tree placement",
Proc. IWLS '07, pp. 336-342.
PDF
A. Mishchenko, R. Brayton, J.-H. R. Jiang, and S. Jang,
"SAT-based logic optimization and resynthesis",
Proc. IWLS '07, pp. 358-364.
PDF
#### FPGA

S. Cho, S. Chatterjee, A. Mishchenko, and R. Brayton,
"Efficient FPGA mapping using priority cuts". (Poster.) Proc. FPGA '07.
PDF
#### Technical reports

A. Mishchenko, S. Chatterjee, and R. Brayton,
"Fast Boolean matching for LUT structures".
ERL Technical Report, EECS Dept., UC Berkeley.
PDF
A. Mishchenko, R. Brayton, J.-H. R. Jiang, and S. Jang,
"SAT-based logic optimization and resynthesis".
ERL Technical Report, EECS Dept., UC Berkeley.
PDF
R. Brayton and A. Mishchenko,
"Scalably-verifiable sequential synthesis",
ERL Technical Report, EECS Dept., UC Berkeley.
PDF
R. Brayton and A. Mishchenko,
"Scalable sequential verification",
ERL Technical Report, EECS Dept., UC Berkeley.
PDF
A. Hurst, A. Mishchenko, and R. Brayton,
"Fast minimum-register retiming via binary maximum-flow",
ERL Technical Report, EECS Dept., UC Berkeley.
PDF
A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, "Cutless FPGA mapping",
ERL Technical Report, EECS Dept., UC Berkeley.
PDF
#### ASP-DAC

Y.-S. Yang, S. Sinha, A. Veneris and R. K. Brayton.
"Automating logic rectification by approximate SPFDs".
Proc. ASP-DAC '07, pp. 402-407.
PDF

## 2006

#### Journals

A. Mishchenko, S. Chatterjee, and R. Brayton,
"Improvements to technology mapping for LUT-based FPGAs".
IEEE TCAD, Vol. 26(2), Feb 2007, pp. 240-253.
PDF
J.-H. Jiang and R. Brayton,
"Retiming and resynthesis: A complexity perspective".
IEEE TCAD, Vol. 25(12), Dec 2006, pp. 2674-2686.
PDF
#### ICCAD

S. Chatterjee, A. Mishchenko, and R. Brayton,
"Factor cuts",
Proc. ICCAD '06, pp. 143-150.
PDF
A. Mishchenko, S. Chatterjee, R. Brayton, and N. Een,
"Improvements to combinational equivalence checking",
Proc. ICCAD '06, pp. 836-843.
PDF
#### DAC

J. S. Zhang, A. Mishchenko, R. Brayton, and M. Chrzanowska-Jeske,
"Symmetry detection for large boolean functions using circuit representation, simulation, and satisfiability",
Proc. DAC '06, pp. 510-515.
PDF
A. Mishchenko, S. Chatterjee, and R. Brayton,
"DAG-aware AIG rewriting: A fresh look at combinational logic synthesis",
Proc. DAC '06, pp. 532-536.
PDF
#### IWLS

S. Chatterjee, A. Mishchenko, and R. Brayton,
"Factor cuts",
Proc. IWLS '06, pp. 1-8. (See ICCAD'06)
M. L.Case, A. Mishchenko, and R. K. Brayton,
"Inductively finding a reachable state space over-approximation",
Proc. IWLS '06, pp. 172-179.
PDF
A. Mishchenko, S. Chatterjee, R. Brayton, and N. Een,
"Improvements to combinational equivalence checking",
Proc. IWLS '06, pp. 180-187. (See ICCAD'06)
A. Mishchenko and R. K. Brayton,
"Scalable logic synthesis using a simple circuit structure",
Proc. IWLS '06, pp. 15-22.
PDF
A. Mishchenko and R. K. Brayton,
"Verification after synthesis",
Proc. IWLS '06, pp. 263-267.
PDF
A. Hurst and R. Brayton,
"Latch-based design under process variation",
Proc. IWLS '06, pp. 241-246.
PDF
#### FPGA

A. Mishchenko, S. Chatterjee, and R. Brayton,
"Improvements to technology mapping for LUT-based FPGAs", Proc. FPGA '06, pp. 41-49.
PDF
#### Technical reports

A. Mishchenko, S. Chatterjee, R. Brayton, and P. Pan,
"Integrating logic synthesis, technology mapping, and retiming",
ERL Technical Report, EECS Dept., UC Berkeley, April 2006.
PDF
G. Wang, A. Mishchenko, R. Brayton, and A. Sangiovanni-Vincentelli,
"Sequential synthesis with co-Buchi specifications",
ERL Technical Report, EECS Dept., UC Berkeley, April 2006.
PDF

## 2005

#### Journals

S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam,
"Reducing structural bias in technology mapping",
IEEE Trans. CAD, Vol. 25(12), December 2006, pp. 2894-2903.
PDF
A. Mishchenko, J. S. Zhang, S. Sinha, J. R. Burch, R. Brayton, and M. Chrzanowska-Jeske,
"Using simulation and satisfiability to compute flexibilities in Boolean networks",
IEEE Trans. CAD, Vol. 25(5), May 2006, pp. 743-755.
PDF
A. Mishchenko and R. Brayton,
"A theory of non-deterministic networks",
IEEE Trans. CAD, Vol. 25(6), June 2006, pp. 977-999.
PDF
A. Aziz, F. Balarin, V. Singhal, R. Brayton, and A. Sangiovanni-Vincentelli,
"Equivalances for Fair Kripke Structures",
Chicago Journal of Theoretical Computer Science, June 2005.
PDF
#### ICCAD

S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam,
"Reducing structural bias in technology mapping",
Proc. ICCAD '05, pp. 519-526.
PDF
Y. Li, A. Kondratyev, R. Brayton,
"Synthesis methodology for built-in at-speed testing",
Proc. ICCAD '05, pp. 183-188.
PDF
#### Fifth Intl. Conf. on Application of Concurrency to System Design, Palais du Grand Large, St Malo, France, June 7-9, 2005

Y. Li, A. Kondrayev, and R. Brayton,
"Gaining predictability and noise immunity in global interconnects",
Proc. ACSD '05.
PDF
#### 14th International Workshop on Logic and Synthesis, Lake Arrowhead, California, June 8-10, 2005

Y. Li, A. Kondratyev, R. Brayton,
"Synthesis methodology for built-in at-speed testing",
Proc. IWLS '05.
PDF
J.-H. Jiang, R. Brayton,
"Retiming and resynthesis: A complexity perspective",
Proc. IWLS '05.
PDF
A. Hurst, R. Brayton,
"Computing clock skew schedules under normal process variation",
Proc. IWLS '05.
PDF
A. Mishchenko, S. Chatterjee, R. Brayton, and M. Ciesielski,
"An integrated technology mapping environment",
Proc. IWLS '05.
PDF
S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam,
"Reducing structural bias in technology mapping",
Proc. IWLS '05.
PDF
J. Zhang, S. Sinha, A. Mishchenko, R. Brayton, and M. Chrzanowska-Jeske,
"Simulation and satisfiability in logic synthesis",
Proc. IWLS '05.
PDF
A. Mishchenko, S. Chatterjee, J.-H. Jiang, and R. Brayton,
"Integrating logic synthesis, technology mapping, and retiming",
Proc. IWLS '05.
PDF
#### Design, Automation and Test in Europe, Munich, Germany, March 7-11, 2005

A. Mishchenko and R. Brayton,
"SAT-based complete don't-care computation for network optimization",
Proc. DATE '05, pp. 418-423.
PDF
A. Mishchenko, R. Brayton, R. Jiang, T. Villa, and N. Yevtushenko,
"Efficient solution of language equations using partitioned representations",
Proc. DATE '05, pp. 412-417.
PDF
#### Technical reports

A. Mishchenko, S. Chatterjee, R. Jiang, and R. Brayton,
"FRAIGs: A unifying representation for logic synthesis and verification".
ERL Technical Report, EECS Dept., UC Berkeley, March 2005.
PDF

## 2004

#### Journals

S. P. Khatri, S. Sinha, R. K. Brayton, and A. L. Sangiovanni-Vincentelli,
"SPFD-based wire removal in standard-cell and network-of-PLA circuits",
IEEE Trans. CAD, Vol. 23(7), July 2004, pp. 1020-1030.
PDF
#### ICCAD

J.-H. R. Jiang, A. Mishchenko, and R. K. Brayton
"On breakable cyclic definitions",
Proc. ICCAD '04, pp. 411-418.
PDF
S. Chatterjee and R. K. Brayton,
"A new incremental placement algorithm and its application to congestion-aware divisor extraction",
Proc. ICCAD '04, pp. 541-548.
PDF
#### DAC

F. Mo and R. K. Brayton,
"A timing-driven module-based chip design flow",
Proc. DAC '04, pp. 67-70.
PDF
#### CAV

J.-H. R. Jiang and R. K. Brayton,
"Functional dependency for verification reduction",
Proc. CAV '04, pp. 268-280.
PDF
#### IWLS

Y. Li, A. Kondratyev, and R. K. Brayton,
"Clockless implementation structure and methodology for DSM implementation",
Proc. IWLS '04, pp. 92-98.
PDF
S. Chatterjee and R. K. Brayton,
"Layout-aware logic decomposition",
Proc. IWLS '04, pp. 155-161. (See ICCAD '04)
J.-H. R. Jiang and R. K. Brayton,
"Functional dependency for verification reduction",
Proc. IWLS '04, pp. 184-191. (See CAV '04)
A. Mishchenko and R. K. Brayton,
"SAT-based complete don't-care computation for network optimization",
Proc. IWLS '04, pp. 353-360.
PDF
A. Mishchenko, R. K. Brayton, J.-H. R. Jiang, T. Villa, and N. Yevtushenko,
"Efficient solution of language equations using partitioned representations",
Proc. IWLS '04, pp. 401-408. (See DATE '05)
N. Yevtushenko, T. Villa, R. K. Brayton, A. Mishchenko, and A. L. Sangiovanni-Vincentelli,
"Composition operators in language equations",
Proc. IWLS '04, pp. 409-415.
PDF
S. Sinha, X. Wang, and R. K. Brayton,
"Comparing two rewiring models",
Proc. IWLS '04, pp. 438-445.
PDF
J.-H. R. Jiang, A. Mishchenko, and R. K. Brayton,
"On breakable cyclic definitions",
Proc. IWLS '04, pp. 454-461. (See ICCAD '04)
#### Books and Book Chapters

F. Mo and R. K. Brayton,
"Regular fabrics in deep sub-micron integrated-circuit design",
Kluwer Academic Publishers, ISBN: 1-4020-8041-7, May 2004.
F. Mo and R. Brayton,
"Structured Digital Design" (book chapter).
In "CRC handbook of EDA for IC Design",
eds. L. Lavagno, G. Martin, and L. Scheffer, CRC Press.
#### Technical Reports

F. Mo and R. Brayton,
"An integrated standard-cell physical design algorithm",
ERL Technical Report, EECS Dept., UC Berkeley, 2004.
PDF

## 2003

#### Journals

F. Mo and R. K. Brayton,
"PLA-based regular structures and their synthesis",
IEEE Trans. CAD, Vol. 22(6), June 2003, pp. 723-729.
PDF
J.-H. R. Jiang, and R. K. Brayton,
"On the verification of sequential equivalence"
IEEE Trans. CAD, Vol. 22(6), June 2003, pp. 686-697.
PDF
V. Singhal, C. Pixley, A. Aziz, S. Qadeer, and R. Brayton,
"Sequential optimization in the absence of global reset",
ACM TODAES, Vol. 8(2), April 2003, pp. 222-251.
PDF
#### ICCAD

A. Mishchenko and R. K. Brayton,
"A theory of non-deterministic networks",
Proc. ICCAD '03, pp. 709-717.
PDF
#### DAC

Y. Jiang, S. Matic, and R. K. Brayton,
"Generalized cofactoring for logic function evaluation",
Proc. DAC '03, pp. 155-158.
PDF
#### DATE

J.-H. R. Jiang, A. Mishchenko, and R. K. Brayton,
"Reducing multi-valued algebraic operations to binary",
Proc. DATE '03, pp. 752-757.
PDF
N. Yevtushenko, T. Villa, R. Brayton, A. Petrenko, and A. Sangiovanni-Vincentelli,
"Equisolvability of series vs. controller's topology in synchronous language equations",
Proc. DATE '03, pp. 1154-1155.
#### IWLS

F. Mo and R. Brayton,
"Checkerboard: A regular structure and its synthesis",
Proc. IWLS '03, pp. 7-13.
PDF
S. Chatterjee and R. Brayton,
"A fast kernel placement algorithm for placement-aware logic synthesis",
Proc. IWLS '03, pp. 14-17. (See ICCAD '04)
R. Jiang and R. Brayton,
"Depth-bounded communication complexity for distributed computation",
Proc. IWLS '03, pp. 51-58.
PDF
N. Yevtushenko, T. Villa, R. Brayton, A. Petrenko, and A. Sangiovanni-Vincentelli,
"Compositionally progressive solutions of synchronous language equations",
Proc. IWLS '03, pp. 148-155.
PDF
Y. Li and R. Brayton,
"Multi-valued optimization on Post logic networks",
Proc. IWLS '03, pp. 220-225.
PDF
A. Mishchenko, R. Brayton, and T. Sasao,
"Exploring multi-valued minimization using binary methods",
Proc. IWLS '03, pp. 278-285.
PDF
R. Brayton and A. Mishchenko,
"A theory of non-deterministic networks",
Proc. IWLS '03, pp. 286-293. (See ICCAD '03)
Y. Jiang and R. Brayton,
"An information theoretic approach to logic evaluation",
Proc. IWLS '03, pp. 341-348.
PDF
#### ISPD

F. Mo and R. K. Brayton,
"Fishbone: A block-level placement and routing scheme",
Proc. ISPD '03, pp. 204-209.
PDF
#### ASP-DAC

Y. Jiang and R. K. Brayton,
"Don't cares in logic minimization of extended finite state machines",
Proc. ASP-DAC '03, pp. 809-815.
PDF
#### Technical reports

N. Yevtushenko, T. Villa, R. Brayton, A. Petrenko, and A. Sangiovanni-Vincentelli,
"Sequential synthesis by language equation solving",
Tech. Rep. UCB/ERL M03/9, 11 April 2003
PDF

## 2002

#### ICCAD

F. Mo and R. Brayton,
"Whirlpool PLAs: A regular logic structure and their synthesis",
Proc. ICCAD '02, pp. 543-550.
PDF
A. Mishchenko and R. K. Brayton,
"Simplification of non-deterministic multi-valued networks",
Proc. ICCAD '02, pp. 557-562.
PDF
S. Sinha, A. Mishchenko, and R. K. Brayton,
"Topologically constrained logic synthesis",
Proc. ICCAD '02, pp. 679-686.
PDF
#### 5th Intl Workshop on Boolean Problems, September 19-20, 2002, Freiberg (Sachsen), Germany

A. Mishchenko and R. Brayton,
"A theory of non-deterministic networks",
Proc. Intl Workshop on Boolean Problems '02. (See ICCAD '03)
#### DAC

F. Mo and R. K. Brayton,
"River PLAs: A regular circuit structure",
Proc. DAC '02, pp. 201-106.
PDF
"Software synthesis from synchronous specifications
using logic simulation techniques",
Y. Jiang and R. K. Brayton,
Proc. DAC '02, pp. 319-324.
PDF
#### IWLS

S. Sinha, A. Mishchenko, and R. K. Brayton.
"Topologically constrained logic synthesis",
Proc. IWLS '02, pp. 13-20. (See ICCAD '02)
A. Mishchenko and R. K. Brayton,
"A Boolean paradigm in multi-valued logic synthesis",
Proc. IWLS '02, pp. 173-177.
PDF
A. Mishchenko and R. K. Brayton,
"Simplification of non-deterministic multi-valued networks",
Proc. IWLS '02, pp. 333-338. (See ICCAD '02)
J.-H. R. Jiang, A. Mishchenko, and R. K. Brayton,
"Reducing multi-valued algebraic operations to binary",
Proc. IWLS '02, pp. 339-344. (See DATE '03)
F. Mo and R. K. Brayton,
"Regular fabrics in deep sub-micron integrated-circuit design",
Proc. IWLS '02.
PDF
J.-H. R. Jiang and R. K. Brayton,
"On the verification of sequential equivalence",
Proc. IWLS '02. (See TCAD '03)
S. Sinha and R. Brayton,
"Topologically constrained logic synthesis",
Proc. IWLS '02. (See ICCAD '02)
N. Yevtushenko, T. Villa, R. Brayton, A. Petrenko, and A. Sangiovanni-Vincentelli,
"Equisolvability of series vs. controller's topology in
synchronous language equations",
Proc. IWLS '02.
PS
#### ISMVL

R. K. Brayton, M. Gao, J.-H. R. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, and T. Villa,
"Optimization of multi-valued multi-level networks",
Proc. ISMVL '02, pp. 168-177.
PDF
#### International Symposium of Hardware/Software Codesign, Estes Park, Colorado

M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, and A. Sangiovanni-Vincentelli,
"HW/SW partitioning and code generation of embedded control
applications on a reconfigurable architecture platform",
Proc. International Symposium of Hardware/Software Codesign (CODES), May 2002.
PDF
#### DATE

E. Goldberg, M. Prasad, and R. Brayton,
"Using problem symmetry in search-based satisfiability",
Proc. DATE '02, pp. 134-141.
PDF
#### Technical reports

A. Mishchenko and R. K. Brayton,
"Higher-order flexibilities in multi-valued networks",
ERL Technical Report, EECS Dept., UC Berkeley, May 2002.
PDF