Motivation – multi-valued devices
*MIN operator
A. Jain, R. Bolton and M. Abd El-Barr, “CMOS Multi-Valued Logic Design”, IEEE Trans. on Circuits and Systems, Aug. 1993.
N
N
x
y
min(x,y)
P
x
I1
I2>0
I3
I4
N
current
mirror
1.New design paradigm and its benefits;
2.It’s basic building blocks;
This shows NMOS only and the same applies for PMOS.
3.This paper shows the design of a fast multiplier. 50% faster than binary CMOS under the same voltage and power consumption.