Threshold detector
PMOS current mirror
Linear sum
Current source
Motivation – multi-valued devices
*Multi-valued current-mode MOS
nsigned digit arithmetic
nHigh-speed, Low supply voltage
T. Hanyu and M. Kameyama, “A 200 MHz pipelined multiplier using 1.5 V-supply
multiple-valued MOS current-mode circuits with dual-rail source-coupled logic”,
IEEE Journal of Solid-Statee Circuits, 1995
A. Jain, R. Bolton and M. Abd El-Barr, “CMOS Multi-Valued Logic Design”, IEEE Trans. on Circuits and Systems, Aug. 1993.
Building blocks
x
y
x+y
vm
m
x
y1
y2
Ix
IT
Iy
1.New design paradigm and its benefits;
2.It’s basic building blocks;
This shows NMOS only and the same applies for PMOS.
3.This paper shows the design of a fast multiplier. 50% faster than binary CMOS under the same voltage and power consumption.