Motivation – synchronous hardware
*Design and synthesis from multi-valued logic
nMV is natural method of specification
nLarger design space
Two-level MV-PLA synthesis
R. Rudell, et al “Espresso-MV”, 1987
Multi-level FSM synthesis (single MV)
L. Lavagno, et al “MIS-MV”, 1990
FSM state encoding
T. Villa, et al, “Nova”, 1990
 E. Goldberg, et al, “Minsk”, 1999
MVSIS 1.1
Verilog-MV
BLIF-MV
MV-Optimize
Opt-Encode
SIS
Encode
vl2mv
Verilog
1.Current design process;
2.Alternative design flow using multi-valued logic;
3.Previous work and why they did not succeed;
1.Optimization hard;
2.Encoding hard
4.MVSIS uniqueness and contribution.