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In this talk I will present the software system we have developed at UC Berkeley called MVSIS for multi-valued logic optimization.
Present the MVSIS group, which include the following members.
1.Time allocation:
1.Motivation ¼
2.Specification and optimization ½
3.Examples and demo ¼
2.
We identified immediate application in these four areas.
1.Current design process;
2.Alternative design flow using multi-valued logic;
3.Previous work and why they did not succeed;
1.Optimization hard;
2.Encoding hard
4.MVSIS uniqueness and contribution.
2.Design flow for Esterel;
3.Previous work and what is lacking;
4.MVSIS contribution.
5.
FIX THE REFERENCE FOR BERRY!
1.New design paradigm and its benefits;
2.It’s basic building blocks;
This shows NMOS only and the same applies for PMOS.
3.This paper shows the design of a fast multiplier. 50% faster than binary CMOS under the same voltage and power consumption.
1.Synchronous hardware computation model;
2.Boolean algebra; however, it can be easily converted into a multi-valued algebra by imposing a priority ordering among the different values.
1.Literal: Boolean function and evaluates to 1 if the variable takes on value 0, or 2;
2.Cube: Boolean product of a set of literals and evaluates to 1 if all literals evaluate to 1.
3.SOP and MDD
1. Exdc output always binary.
The optimization sequence is:
1.Derive the kernel/cubes;
2.Divide it into the original expressions;
3.Substitute into other expressions;
Different flavors of commands developed around this concept, like in SIS.
Define: non-determinism is the specification allows the same input minterm to produce different values at the primary output.
Define: don’t care is a minterm that is not specified and the output is allowed to produce any value.
Value of a part/node: the cost associated with this part/node, if eliminated, the cost being literal count or cube count.
1.New design paradigm and its benefits;
2.It’s basic building blocks;
This shows NMOS only and the same applies for PMOS.
3.This paper shows the design of a fast multiplier. 50% faster than binary CMOS under the same voltage and power consumption.