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UC Berkeley EECS 219B (NTU number = DS 763CA) - Robert Brayton

This course is an advanced course in the logic synthesis of digital system designs. It has been the training ground for most of the Berkeley graduate CAD students and is taught typically to first year graduate students and CAD visitors every spring at Berkeley. Emphasis is placed on the methods for representation and manipulation (including optimization) of logic. These methods form the basis of most modern logic synthesis and verification systems. The class starts with the basic notions of logic functions and their representation in sum-of-products (SOP) form. Minimization of such forms focuses on the more fundamental algorithms which reappear in the latter parts of the course. Both combinational and sequential logic are discussed. Methods for representation and analysis of logic include the classical SOP and POS forms, binary decision diagrams (BDD's), multi-level circuits, SAT clauses, state transition graphs, and state transition relations. Extensions from binary-valued logic to multi-valued logic allow generalizations to analysis and solution of discrete functions of discrete valued variables, suggesting a wide variety of applications to discrete optimization problems such as graph optimization, VLSI physical design, and behavioral optimization. Interrelations between logic synthesis and different CAD specialties such as testing, delay analysis/testing, verification, and software compilation will be developed.

The goal of this course is to provide the student with a working repertoire of different methods for logic representation, manipulation, and optimization, for both combinational and sequential logic. At the end of the course the student should be able to view the design of digital systems from a new perspective and have access and understanding of a suite of powerful tools that can be applied to a wide variety of CAD for VLSI problems.

This course covers the synthesis of logic functions at an advanced level. The course starts with basic theory and develops towards the most modern methods where practical issues of efficiency and optimality in terms of area, speed, power and testability are considered. Some of the methods covered are: exact and heuristic methods for two-level logic minimization, multi-valued minimization, equivalence checking, multi-level logic optimization for area performance and testability, test pattern generation and redundancy removal, timing analysis, false path removal, delay testing, state assignment and state minimization, retiming, and sequential verification and testing.

43 hours of instruction.

(MWF 1 hour; color) Spring 1997

The course requires some mathematical sophistication. A course or practical experience in digital logic design is recommended.

Reader of selected papers.

Course notes and reprints on material not covered in the Reader will be supplied by the Cal View program office at no charge. A complete set of transparencies for the entire course can be viewed at http://www-cad.EECS.Berkeley.EDU/HomePages/brayton/courses/219b/219b.html

approximately 9 homework assignments

2 mid-terms and 1 final exam.

The Berkeley synthesis system SIS and the logic minimization program ESPRESSO are part of the homework problems and the subject of some of the lectures. The student should have access to these programs which are available by anonymous FTP over the web.


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Robert K. Brayton
Mon Dec 16 15:27:51 PST 1996