4.1.1 Two-Level (1982 – 1987)
4.1.2 Multi-level –
Technology Independent (1981 – 2001)
4.1.3
Incremental Re-Synthesis – Engineering Change (1991 – 1997)
4.1.4
BDDs, SAT, Covering Problems etc. (1989 – 2002)
4.1.5
Technology Mapping and FPGA Synthesis (1980 – 2000)
4.1.6
Delay Optimization (1988 – 1994)
4.1.7
Flexibilities – Don’t Cares and SPFDs (1986 – 2002)
4.1.8
Asynchronous (1990 – 1994)
4.1.9
Multi-Valued Logic (1990 – 2002)
4.2.1
State Assignment, State Minimization, and Encoding (1984 – 1997)
4.2.2
Retiming (1990 – 2001)
4.2.3
Sequential Flexibility (1993 – 2002)
4.2.4
General (1990 – 2002)
6.1
Testing (1990 – 1997)
6.2 Equivalence Checking
(1988 – 2002)
6.3 Model Checking (1991 –
2002)
1.
R.K. Brayton, "On the Asymptotic Behavior of the
Number of Trials Necessary to Complete a Set with Random Selection," Ph.D.
Thesis, M.I.T., September 1961 and J. of Mathematical Analysis and Applications
7, 1, pp. 31-61, August 1963. PhD Thesis
2.
R.K. Brayton and W.L. Miranker, "A Stability Theory
for Nonlinear Mixed Initial Boundary Value Problems," RC-1021, IBM
Research Center, Yorktown Heights, NY, August 1963 and Arch. Ratl. Mech. and
Anal. 17, 5, 358-376, December 1964.
3.
R.K. Brayton, F. Gustavson and W. Liniger,
"Numerical Analysis of the Transient Behavior of a Transistor
Circuit," RC-1193 IBM Research Center, Yorktown Heights, NY, May 1964 and
IBM Journal of Research and Development 10, 4, 292-299, July 1966.
4.
R.K. Brayton, "Bifurcation of Periodic Solutions in
a Nonlinear Difference- Differential Equation," RC 1427, IBM Research
Center, Yorktown Heights, NY, June 1965 and Applications of Mathematics, XXIV,
No. 3, pp. 215-224, October 1966.
5.
R.K. Brayton and R.A. Willoughby, "On the Numerical
Integration of a Symmetric System of Difference-Differential Equations of
Neutral Type," RC 1507, IBM Research Center, Yorktown Heights, NY,
December 1965 and Journal of Mathematical Analysis and Applications, 18,
182-189, 1967.
6.
R.K. Brayton, "On the Bifurcation of Periodic
Solutions in Nonlinear Difference-Differential Equations of Neutral Type,"
Proceedings of Symposium on Differential Equations and Dynamical Systems,
Puerto Rico, Academic Press, 1967.
7.
R.K. Brayton, Fred G. Gustavson and Ralph A. Willoughby,
"Some Results on Space Matrices," Sparse Matrix Proceedings,
Yorktown, NY, pp. 43-58, September 1968.
8.
R.K. Brayton, F. G. Gustavson and R. A. Willoughby,
"Some Results on Sparse Matrices," RC 2332, February 1969, IBM
Research Center, Yorktown Heights, NY, Math. Comp. 24, 112, pp. 937-954,
October 1970.
9.
R.K. Brayton, "Necessary and Sufficient Conditions
for Bounded Global Stability of Certain Nonlinear Systems," RC 2623, IBM
Research Center, Yorktown Heights, NY, September 1969, Applications of
Mathematics, pp. 237-244, July 1971.
10.
R.K. Brayton, "Totally Unimodular Matrices which are
Path-Branch Incidence Matrices of Directed Trees," RC-2849, IBM Research
Center, Yorktown Heights, NY, April 1970.
11.
R.K. Brayton, "The Use of the ASTAP Language for
General Model Simulation," IBM Technical Memorandum, June 1970.
12.
R.K. Brayton, "Necessary and Sufficient Conditions
for Bounded Global Stability of Certain Nonlinear Systems," Proceedings
Kyoto International Conference on Circuit and Systems, Kyoto, Japan, September
1970.
13.
R.K. Brayton, F.G. Gustavson and G.D. Hachtel , “A New
Efficient Algorithm for Solving Differential-Algebraic Systems Using Implicit
Backward Differentiation Formulae”, RC-3381, IBM Research Center, Yorktown
Heights, NY, June 1971; Proceedings of IEEE, pp. 98-108, January 1972.
14.
W.L. Miranker and R.K. Brayton, "Notes for a Short
Course in Mathematical Modeling and Computer Techniques," NSF Chautauqua
Short Courses for College Teachers, 1972.
15.
R.K. Brayton and C.C. Conley, "Some Results on the
Stability and Instability of the Backward Differentiation Methods with
Non-Uniform Time Steps," IBM Research Report RC-3964, July 1972,
Proceedings of International Symposium on Numerical Analysis, Dublin, Ireland,
August 1972.
16.
R.K. Brayton, F.G. Gustavson and G.D. Hachtel, "A
New Efficient Algorithm for Solving Differential-Algebraic Systems Using
Implicit Backward Differentiation Formulae," Computer-Aided Circuit
Design, Simulation and Optimization, edited by S. W. Director, Series Benchmark
Papers in Electrical Engineering and Computer Science, Dowden Hutchinson and
Ross, Inc., Stroudsburg, PA, 1973.
17.
R.K. Brayton, "Numerical A-Stability for
Difference-Differential Systems," IBM Research Report, RC-4647, December
1973, Proceedings of the International Symposium on Stiff Differential Systems,
Wildbad, Germany, October 4-6, 1973.
18.
R.K. Brayton, D. Coppersmith and A.J. Hoffman,
"Self-Orthogonal Latin Squares," IBM Research Report, RC-4532,
September 1973.
19.
R.K. Brayton, Alan J. Hoffman and Don Coppersmith,
"Self-orthogonal Latin Squares," Colloquia Internazionalle sulle
TEORIE COMBINATORIE, September 3-15, 1973; Academia Nazionale Dei Lincei, Roma,
pp. 509-517, 1976.
20.
R.K. Brayton, A.J. Hoffman and D. Coppersmith,
"Self-orthogonal Latin Squares of All orders n Except n=2,3,6," IBM
Research Report RC-4532; Bulletin of AMS, Volume 80, No. 1, January 1974.
21.
R.K. Brayton, "Recognition of Hand-Printed
Materials," IBM Technical Memo, April 1976.
22.
R.K. Brayton and C.H. Tong, "Stability of Dynamical
Systems: A Constructive Approach," IBM Research Report RC-7027, February
1978; Proceedings of IEEE International Symposium on Circuits and Systems, May
1978.
23.
G.M. Shepherd and R.K. Brayton, "Analysis of
Dendrodendritic Synaptic Circuit by Computer Simulation," IBM Research
Report RC-7344, October 1978; Brain Research, 175, pp. 377-382, 1979.
24.
R.K. Brayton and C.H. Tong, "Stability of Dynamical
Systems: A Constructive Approach," IEEE Transactions on Circuits and
Systems, CAS-26, pp. 224-234, April 1979.
25.
R.K. Brayton and C.H. Tong , “Constructive Stability and
Asymptotic Stability of Dynamical Systems”, IBM Research Report RC-7909,
October 1979; Proceedings of the International Symposium on Circuits and
Systems, Tokyo, pp. 573-576, 1979; IEEE Transactions on Circuits and Systems,
November 1980.
26.
R.K. Brayton and C. Tong , “Constructive Stability of
Dynamical Systems”, IEEE Conference on Decision and Control Proceedings,
December 1981.
27.
G.M. Shepherd, R.K. Brayton, J.P. Miller, I. Segev, J.
Rinzel and W. Rall , “Signal Enhancement in Distal Dendrites by Means of
Interactions Between Active Dendritic Spines”, Proceedings of the National
Academy of Science, pp. 2192-2195, April 1985.
28.
G.M. Shepherd and R.K. Brayton , “Logic Operations are
Properties of Computer-Simulated Interactions Between Excitable Dendritic
Spines”, IBM Research Report, RC-11804, March 1986.
29.
G.M. Shepherd and R.K. Brayton , “Logic Operations are
Properties of Computer-Simulated Interactions Between Excitable Dendritic
Spines”, Neuroscience 1987 pp 151-165.
30.
R.K. Brayton, "Estimates on Switching Time in a
Circuit Containing One Esaki Diode," RC-338, IBM Research Center, Yorktown
Heights, NY, September 1960.
31.
R.K. Brayton and R. Willoughby, "An Analysis of the
Effect of Component Tolerances on the Amplification of the Balanced-Pair Tunnel
Diode Circuit," RC-673, IBM Research Center, Yorktown Heights, NY, IEEE
Transactions on Electronics and Computers, EC-12, 3, pp. 269-274, June 1963.
32.
R.K. Brayton, W.L. Miranker and R.A. Toupin, "A
Numerical Analysis of a Magneto-Resistive Circuit Employed as a Voltage
Regulator," NC-295, IBM Research Center, Yorktown Heights, NY, September
1963.
33.
R.K. Brayton, "Some Results on the Stability of
Nonlinear Networks Containing Negative Resistances," IEEE Transactions on
Circuit Theory, CT-11, 165-167, March 1964.
34.
R.K. Brayton and J.K. Moser, "A Theory of Nonlinear
Networks, Part I," Applications of Mathematics, XXII, 1 1-33, April 1964.
35.
R.K. Brayton and J.K. Moser, "A Theory of Nonlinear
Networks, Part II," Applications of Mathematics, XXII, 2, 81-104, July
1964.
36.
R.K. Brayton, "Stability Criteria for Large Networks,"
IBM Journal of Research and Development 8, 4, 466-470, September 1964.
37.
R.K. Brayton, "On the Effect of Component Tolerances
in the Balanced- Pair Tunnel-Diode Circuit," IEEE Transactions on Circuit
Theory CT-11, 351-356, September 1964.
38.
R.K. Brayton, "A Canonical Form for Nonlinear RLC
Networks," Proceedings, Symposium on System Theory, Polytechnic Institute
of Brooklyn, NY, April 1965.
39.
R.K. Brayton, "Nonlinear Oscillations in a
Distributed Network," RC-1405, IBM Research Center, Yorktown Heights, NY,
April 1965, Applications of Mathematics XXIV, No. 4, pp. 289-301, January 1967.
40.
R.K. Brayton, "A Small-signal Stability Criterion
for Electrical Networks Containing Lossless Transmission Lines," RC 1686,
IBM Research Center, Yorktown Heights, NY, September 1966, IBM Journal of
Research and Development, pp.431-440, November 1968.
41.
R.K. Brayton, "The Termination Condition for No
Reflection and Infinite Directivity in a Lossles System of Parallel
Conductors," NC-631, IBM Research Center, Yorktown Heights, NY, July 1966.
42.
R.K. Brayton, G.D. Hachtel, F.G. Gustavson and T. Grapes,
"A Sparse Matrix Approach to Network Analysis," RC-2646 IBM Research
Center, Yorktown Heights, NY, August 1969, Proceedings of Second Biannual
Cornell Conference on Computerized Electronics, October 1969.
43.
R.K. Brayton, "Nonlinear Reciprocal Networks,"
RC 2606 September 1969, IBM Research Center, Yorktown Heights, NY, Proceedings
of SIAM-AMS Symposium on Electrical Network Theory, Vol. III, pp. 1-16, 1971.
44.
G.D. Hachtel, R.K. Brayton and F.G. Gustavson, "The
Sparse Tableau Approach to Network Analysis and Design," RC 3008, IBM
Research Center, Yorktown Heights, NY, May 1970 and IEEE Transactions of
Circuit Theory, Vol. CT-18, pp. 111-113, January 1971; The World of Large Scale
Systems, IEEE Press, pp. 4-16, 1982.
45.
R.K. Brayton, Fred G. Gustavson and Gary D. Hachtel,
"A Sparse Tableau Matrix Approach to Network Analysis and Design,"
Chiao Tung Colloquium on Circuits and Systems, Taiwan, Republic of China,
August 1970.
46.
G.D. Hachtel, R.K. Brayton and F.G. Gustavson,
"Large-scale Network Computations Via the Sparse Tableau Approach,"
1970 International Symposium on Circuit Theory, Atlanta, Ha., December 1970,
Digest of Technical Papers, edited by Lewis Winner, New York, pp. 163-164,
1970.
47.
R.K. Brayton, F. G. Gustavson and G. D. Hachtel,
"The Use of Variable-Order Variable-Step Backward Differentiation Methods
for Nonlinear Electrical Networks," Proceedings of IEEE Mexico Conference,
January 1971.
48.
G.D. Hachtel, R.K. Brayton and F.G. Gustavson,
"Sparse Tableau Approach to Nonlinear Adjoint Sensitivity
Computations," Proceedings of IEEE Mexico Conference, January 1971.
49.
G.D. Hachtel, R.K. Brayton and F.G. Gustavson, "The
Sparse Tableau Approach to Network Analysis and Design," Computer-Aided
Circuit Design, Simulation and Optimization, Edited by S.W. Director, Series
Benchmark Papers in Electrical Engineering and Computer Science, Dowden
Hutchinson and Ross, Inc., Stroudsburg, PA, 1973.
50.
R.K. Brayton and S.W. Director, "The Event
Functional and Its Use in Time Domain Optimization," IBM Research Report
RC-5209, February 1975; Proceedings of the International Symposium on Circuits
and Systems, Boston, Mass, April 1975.
51.
R.K. Brayton and S.W. Director, "Computation of
Delay Time Sensitivities for Use in Time Domain Optimization," IEEE
Transactions on Circuits and Systems, Volume CAS-22, No. 12, pp. 910-920,
December 1975.
52.
R.K. Brayton, A.J. Hoffman and T.R. Scott, "A
Theorem on Inverses of Convex Sets of Real Matrices with Application to the
Worst Case DC Problem," Proceedings of the International Symposium on
Circuits and Systems, pp. 82-85, April 1976; IEEE Transactions on Circuits and
Systems, Volume CAS-24, No. 8, pp. 409-415, August 1977.
53.
R.K. Brayton, "Tolerance Assignment and Design
Centering in the Convex Case," IBM Research Report RC-5964, April 1976.
54.
Jane Cullum and R.K. Brayton, "Some Remarks on the
Symmetric Rank One Update," IBM Research Report RC-6157, August 1976;
JOTA, 29, pp. 493-519, December 1979.
55.
R.K. Brayton, "Error Estimates for the Variable-step
Backward Differentiation Methods," IBM Research Report RC-6205, September
1976.
56.
R.K. Brayton and Jane Cullum, "An Algorithm for
Minimizing a Differentiable Function Subject to Box Constraints and
Errors," IBM Research Report RC-6429, March 1977; Proceedings of IEEE
Conference on Decision and Control, December 1976; Proceedings of IEEE
International Symposium on Circuits and Systems, April 1977; JOTA, 29, pp.
521-558, December 1979.
57.
R.K. Brayton and Jane Cullum, "Optimization with the
Parameters Constrained to a Box," Numerical Methods for Differential
Equations and Simulation, North-Holland, 1978.
58.
R.K. Brayton, L.O. Chua, J.D. Rhodes and R. Spence,
"Modern Network Theory-An Introduction," Optimization in Computer
Aided Circuit Design, Georgi Publishing Co. 1978. Book
59.
R.K. Brayton, S.W. Director and G.D. Hachtel,
"Arbitrary Norms for Statistical Design via Linear Programming,"
Proceedings of IEEE International Symposium on Circuits and Systems, May 1978.
60.
R.K. Brayton, S.W. Director, G.D. Hachtel and L.M.
Vidigal, "Yield Maximization and Tolerance Assignment Via Simplicial
Approximation," Proceedings of Electro '78, May 1978.
61.
R.K. Brayton, "Optimization in Computer Aided
Circuit Design," IBM Research Report RC-7159; 1978 European Conference on
Circuit Theory and Design, Volume II-Guest Lectures, pp. 7-63, September 1978.
62.
R.K. Brayton, S.W. Director and G.D. Hachtel, "Yield
Maximization and Worst-Case Design with Arbitrary Statistical
Distributions," IBM Research Report RC-7506, February 1979; IEEE
Transactions on Circuits and Systems, CAS-26, September 1979.
63.
R.K. Brayton, S.W. Director, G.D. Hachtel and L.M.
Vidigal, "A New Algorithm for Statistical Circuit Design Based on
Quasi-Newton Methods and Function Splitting," IBM Research Report RC-7702,
June 1979; Proceedings of IEEE International Symposium on Circuits and Systems,
Tokyo, pp. 280-283, July 1979.
64.
R.K. Brayton, and C.H. Tong , “Some Results on the
Nonlinear Worst-Case Problem”, Proceedings of the IEEE International Symposium
on Circuits and Systems, pp. 1142, April 1980.
65.
R.K. Brayton and R. Spence , “Computer-Aided Circuit
Design: Sensitivity and Optimization”, Elsevier Scientific Publishing Co.,
Amsterdam, 1981. Book
66.
R. Brayton, G. Hachtel and A. Sangiovanni-Vincentelli, A
Survey of Optimization Techniques for Integrated Circuit Design, Proceedings of
IEEE, pp. 1336-1361, October 1981, Invited
Paper.
4.1.1 Two-Level (1982 – 1987)
67.
R.K. Brayton, J. Cohen, G.D. Hachtel, B. Trager and
D.Y.Y. Yun , “Fast Recursive Boolean Function Manipulation”, Proceedings of the
International Symposium on Circuits and Systems, April 1982; IBM Corporate
Symposium on Structured Logic, November 1982.
68.
R.K. Brayton, G.D. Hachtel, L. Hemanchandra, R. Newton
and A. Sangiovanni- Vincentelli , “A Comparison of Logic Minimization
Strategies Using ESPRESSO: An APL Program Package for Partitioned Logic
Minimization”, Proceedings of the International Symposium on Circuits and
Systems, pp. 42-48, Rome, Italy, April 1982.
69.
R. Brayton, G. Hachtel, C. McMullen and A.
Sangiovanni-Vincentelli, ESPRESSO-II: A New Logic Minimizer for Programmable
Logic Arrays Proc. 1984 Custom Integrated Circuits Conference, May 1984.
70.
R. Brayton, G. Hachtel, C. McMullen and A.
Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis
Kluwer Academic Publishers, 1984. Book
71.
R. Brayton, A. Malik, A. R. Newton and A.
Sangiovanni-Vincentelli, A Modified Approach to Two-Level Logic Minimization,
Proc. 1988 Int. Conference. on CAD, pp. 106-109, Santa Clara, CA. November
1988.
72.
R.K. Brayton and F. Somenzi, An Exact Minimizer for
Boolean Relations, IEEE International Conference Computer Aided Design,
November 1989.
73.
R.K. Brayton and F. Somenzi, Minimization of Boolean
Relations, Proc. Int. Symp. Circ. Syst. ISCAS, May 1989.
74.
H. Savoj, A. Malik and R.K. Brayton, Fast Two-Level
Minimizers for Multilevel Logic Synthesis, Proceedings of the IEEE
International Conference on Computer Aided Design, November 1989.
75.
A.A. Malik, R. Brayton, A.R. Newton and A.
Sangiovanni-Vincentelli, Reduced Offsets for Two-Level Multi-Valued Logic
Minimization, Proc. of 1990 27th ACM/IEEE Design Automation Conference, pp.
290-296, June 1990.
76.
A.Malik, R. Brayton, A.R. Newton and A.
Sangiovanni-Vincentelli, Two Level Minimization of Multi-Valued Functions Large
Offset, Research Report No. 16112, IBM, Yorktown, September 1990.
77.
A. Malik, R. Brayton, A.R. Newton and A.
Sangiovanni-Vincentelli, Reduced Offset for Minimization of Binary-valued
Functions, IEEE Trans. on CAD of ICAS, Vol. 10, No. 4, pp. 413-426, April 1991.
78.
Y. Watanabe and R.K. Brayton, Heuristic Minimization of
Boolean Relations, International Workshop on the Logic Synthesis, Research
Triangle Park, May 1991.
79.
R. K. Brayton, P. C. McGeer and J. Sanghavi, "A New
Exact and Heuristic Minimizer for two-Level Logic Synthesis," Proceedings of
the International Symposium of the Kyushu Institute of Technology, July 1992.
80.
P. McGeer, J. Sanghavi, R. K. Brayton and A.
Sangiovanni-Vincentelli, "Minimization of Logic Functions Using Essential
Signature Sets," Proc. 6th International Conference on VLSI India, January
1993, [Best paper].
81.
P. C. McGeer, J. Sanghavi, R. K. Brayton and A.
Sangiovanni-Vincentelli, "An Algorithm for Verifying the Equality of
Signature Cubes," Proceedings of the International Workshop on Logic
Synthesis, May 1993.
82.
G. M. Swamy, R. K. Brayton and P. McGeer, "A Fully
Implicit Quine-McClusky Procedure Using BDD'S," International Workshop on
Logic Synthesis, May 1993 and ERL Memo UCB/ERL M92/127.
83.
P. McGeer, J. Sanghavi, R.K. Brayton and A.
Sangiovanni-Vincentelli , “ESPRESSO-Signature: A New Exact Minimizer for Logic
Functions”, Proceedings of the 30th ACM/IEEE Design Automation Conference, pp.
618-624, Dallas, Texas, June 1993 and IEEE Transactions on Very Large System
Integration (VLSI) Systems, Vol. 1, No. 4, pp. 432-440, December 1993.
84.
R. Murgai, R.K. Brayton and A. Sangiovanni-Vincentelli ,
“Cube-packing and Two-Level Minimization”, Proceedings of the IEEE/ACM
International Conference on CAD, pp. 115-122, Santa Clara, CA November 1993.
85.
T. Villa, A. Saldanha, R. K. Brayton, and A. Sangiovanni-Vincentelli, Symbolic
two-level minimization., IEEE Trans. on CAD, vol.16, (no.7), July 1997.
p.692-708
4.1.2 Multi-level – Technology Independent (1981 – 2001)
86.
R. Brayton, G. Hachtel and A. Sangiovanni-Vincentelli,
Taxonomy of CAD for VLSI, with Proceedings of the 1981 ECCTD, La Hague, Invited
Paper, state-of-the-art review lecture.
87.
R.K. Brayton and C. McMullen , “The Decomposition and
Factorization of Boolean Expressions”, Proceedings of the International
Symposium on Circuits and Systems, April 1982.
88.
R. K. Brayton and C. McMullen , “Automatic Implementation
of Logic”, IBM Corporate Symposium on
Structured Logic, November 1982.
89.
R.K. Brayton and C.T. McMullen, “DESIGN User's Manual for
the Yorktown Logic Editor (YLE)” IBM Technical Memo, 1983.
90.
R.K. Brayton and C.T. McMullen , “Synthesis and
Optimization of Multistage Logic”, ICCD '84, Portchester, NY, October 1984.
91.
R.K. Brayton, N.L. Brenner, C.L. hen, G. DeMicheli, C.T.
McMullen and R.H.J.M. Otten , “The YORKTOWN Silicon Compiler”, International
Symposium on Circuits and Systems 1985, Kyoto, Japan, June 1985.
92.
R.K. Brayton, C.L. Chen, G. DeMicheli, J. Katzenelson,
C.T. McMullen, R.H.J.M. Otten and R.L. Rudell, “A Microprocessor Design Using
the Yorktown Silicon Compiler”, ICCD '85, pp. 225-231, October 1985.
93.
R.K. Brayton, E.Detjens, S. Krishna, T. Ma, P. McGeer, L.
Pei, N. Phillips, R. Rudell, R. Segal, A. Wang, R. Yung and A.
Sangiovanni-Vincentelli , “Multiple-Level Logic Optimization System”, IEEE
1986.
94.
R.K. Brayton , “Algorithms for Optimizing Silicon
Compilers”, Proceedings of Automated Design and Engineering for
Electronics-Japan, Tokyo, Japan, January 1986.
95.
R.K. Brayton , “Factoring Logic Functions”, IBM Journal
of Research and Development, May 1986.
96.
R.K. Brayton, “Algorithms for Multi-Level Logic Synthesis
and Optimization”, IBM Research Report RC-11938, July 1986. L'Aquila, Italy,
July 1986; Design Systems for VLSI Circuits: Logic Synthesis and Silicon
Compilation, (ed. P. Antognetti, G. de Micheli, A. Sangiovanni-Vincentelli, M. Nijhoff),
pp.197-249, 1987.
97.
R. Brayton, E. Detjens, S. Krishna, T. Ma, P. McGeer, L.
Pei, N. Phillips, R. Rudell, A. Sangiovanni-Vincentelli, R. Segal, A. Wang, R.
Yung, Multiple-Level Logic Optimization System, International Conference on
Computer-aided Design, Santa Clara, October 1986.
98.
R. Brayton, G. Hachtel, C. McMullen, R. Rudell and A.
Sangiovanni-Vincentelli, Multi-level Logic Optimization Algorithms for VLSI
Synthesis, Kluwer Academic Publisher, 1986.
99.
R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli and
A. Wang , “Multi-Level Logic Optimization and The Rectangle Covering Problem”,
Proceedings of the 1987 IEEE International Conference on Computer-Aided Design,
Santa Clara, November 1987.
100. R. Brayton, R. Rudell, A.
Sangiovanni-Vincentelli and A. Wang, MIS: A Multiple-Level Logic Optimization
System, IEEE Trans. on CAD/ICAS, Vol. CAD-6, No. 6, pp.1062-1082, November
1987.
101. R.K. Brayton R.
Camposano, G. DeMicheli, R.H.J.M. Otten and J. van Eindhoven , “The Yorktown
Silicon Compiler”, IBM Research Report RC-12500; Silicon Compilation edited by
D.D. Gajski, Addison-Wesley, 1988.
102. R.K. Brayton and A.
Sangiovanni-Vincentelli, Logic Research at Berkeley, SRC TECHCON, Dallas Texas,
July 1988.
103. P. McGeer and R.K.
Brayton, Efficient Prime Factorization of Logic Expressions, Design Automation
Conference, June 1989.
104. A. Malik, R.K. Brayton
and A. Sangiovanni-Vincentelli, Logic Minimization for Factored Forms, Proc.
1989 Int. Conference. on Comp. Design, Boston, pp. 396-399, October 1989.
105. R. Brayton, G. Hachtel
and A. Sangiovanni-Vincentelli, Multilevel Logic Synthesis, Proceedings of the
IEEE, Vol. 78, No. 2, pp. 264-300, February 1990 Invited Paper.
106. R. Murgai, R.K. Brayton
and A. Sangiovanni-Vincentelli, “Optimum Functional Decomposition Using
Encoding”, Proceedings of the 31st ACM/IEEE Design Automation Conference, pp.
408-414, San Diego, CA June 1994.
107. Szu-Tsung Cheng, Robert
K. Brayton, "Synthesizing Multi-Phase HDL Programs", Proceedings of
International Verilog Conference, 1996.
108. S. P. Khatri, R. K. Brayton,
and A. L. Sangiovanni-Vincentelli, A VLSI
Design Methodology using a Network of PLAs embedded in a Regular Layout Fabric
IEEE/ACM International Conference on CAD, ICCAD 00,
109. Yunjian Jiang; Brayton, R.K. Logic optimization and
code generation for embedded control applications Ninth International
Symposium on Hardware/Software Codesign. CODES 2001
110. R. Brayton, “The Future of Logic Synthesis and
Verification”, Logic Synthesis and
Verification, S. Hassoun, T. Sasao (editors) R. Brayton (consulting
editor), Kluwer Academic Press, 2001 book
chapter
4.1.3 Incremental Re-Synthesis –
Engineering Change (1991 – 1997)
111. Y. Watanabe and R. K.
Brayton, Incremental Synthesis for Engineering Changes, International Workshop
on the Logic Synthesis, Research Triangle Park, May 1991, International
Conference on Computer Design, Boston, October 1991.
112. Y. Watanabe and R. K.
Brayton, Incremental Synthesis for Engineering Changes, IEICE Transactions Vol.
J74-A, No.2, pp162-169, February 1991.
113. Y. Kukimoto, M. Fujita
and R.K. Brayton , “A Redesign Technique for Combinational Circuits Based on
Gate Reconnections”, Proceedings of the IEEE/ACM Conference on CAD, pp.
632-637, San Jose, CA November 1994.
114. G. M. Swamy, S. Rajamani,
C. Lennard and R. K. Brayton, "Minimal Logic Re-Synthesis", Technical
Report UCB/ERL M96/22, Electronics Res. Lab., University of California,
Berkeley, CA 94720
115. G. Swamy,
4.1.4 BDDs, SAT, Covering Problems etc.
(1989 – 2002)
116. S. Malik, R. Brayton and
A. Sangiovanni-Vincentelli, Encoding Symbolic Inputs for Multi-level Logic
Implementation, Proc. VLSI 89 IFIP Conference, Munich, pp. 221-230, August
1989.
117. A. Saldanha, T. Villa, R.
K. Brayton and A. Sangiovanni-Vincentelli, A Framework for Satisfying Input and
Output Encoding Constraints, Proc. 28th ACM/IEEE DAC Conference, San Francisco,
pp. 170-175, June 1991.
118. P. McGeer, H. Savoj, R.
K. Brayton and A. Sangiovanni-Vincentelli, "Minimizing Logic Functions
Through Binary Decision Diagrams," DAC'92, June 1992.
119. W. Lam and R. K. Brayton,
"On Relationship Between ITE and BDD," International Conference on
Computer Design '92, Boston, Massachusetts, October 1992.
120. W. Lam and R. K. Brayton,
"Some Properties of If-Then-Else DAG's," DAC'92, June 1992.
121. A. Aziz, S. Tasiran and
R. K. Brayton, “BDD Variable Ordering for Interacting Finite State Machines”,
Intl. Workshop on Logic Synthesis, Tahoe City, CA May 1993, Memorandum No.
UCB/ERL M93/71 October 1993 and Proceedings of the 31st IEEE/ACM Design
Automation Conference, pp. 283-288, San Diego, CA June 1994.
122. E. Felt, G. York, R.K.
Brayton and A. Sangiovanni-Vincentelli , “Dynamic Variable Reordering for BDD
Minimization”, Proceedings of the European Design Automation Conference with
EURO-VHDL'93, pp.130-135, CCH Hamburg, Germany September 1993.
123. T. Shiple, R.K. Brayton
and A. Sangiovanni-Vincentelli , “Computing Boolean Expressions with
OBDDs”, Memorandum No. UCB/ERL M93/84
December 1993.
124. T. Shiple, R. Hojati,
R.K. Brayton and A. Sangiovanni-Vincentelli , “Heuristic Minimization of BDDs
Using Don't Cares”, Memorandum No. UCB/ERL M93/58, July 1993 and Proceedings of
the 31st IEEE/ACM Design Automation Conference, pp. 225-231, San Diego, CA June
1994.
125. A. Narayaan, S. Khatri,
J. Jain, M. Fujita, R. Brayton, and A. Sangiovanni-Vincentelli,
"Compositional Techniques for Mixed Bottom-Up/Top-Down construction of
ROBDDs", Tech. Report UCB/ERL M95.51, June 1995.
126. A. Narayaan, S. Khatri,
J. Jain, M. Fujita, R. Brayton, and A. Sangiovanni-Vincentelli, "A Study
of Compositional Schemes for Mixed Apply/Compose Based Constructions of ROBDDs",
Int. Conf on VLSI Design, India, Jan. 1995.
127. M. Fujita and Y. Kukimoto
and R. K. Brayton, "BDD Minimization by Truth Table Permutations",
Proceedings of International Conference on Circuits and Systems, 596-599, IV,
May, 1996
128. J. Jain, Narayan, Coelho,
Khatri, Sangiovanni-Vincentelli, Brayton, Fujita. "Decomposition Techniques
for Efficient ROBDD Construction" Presented at the International
Conference on Formal Methods in Computer-Aided Design, Palo Alto, CA, Nov 1996.
129. Jagesh V. Sanghavi and
Rajeev K. Ranjan and Robert. K. Brayton and Alberto Sangiovanni-Vincentelli,
"High Performance BDD Package Based on Exploiting Memory Hierarchy",
DAC, June, 1996
130. Rajeev K. Ranjan and
Jagesh V. Sanghavi and Robert. K. Brayton and Alberto Sangiovanni-Vincentelli,
"Using Network of Workstations for Efficient Binary Decision Diagram
Manipulation", ICCD, Austin, Texas, USA, October, 1996
131. R. Ranjan, W. Gosti, R.
Brayton, A. Sangiovanni-Vincentelli, "Dynamic Reordering in a
Breadth-First Manipulation Based BDD Package: Challenges and Solutions",
International Workshop on Logic Synthesis (IWLS), May 1997.
132. A. Narayan, A. Isles, J.
Jain, R. Brayton, A. Sangiovanni-Vincentelli, Reachability Analysis Using
Partitioned-ROBDDs, IEEE/ACM International
Conference on CAD, ICCAD 97, pp. 388-393, November 1997.
133. E. I. Goldberg, Y. Kukimoto, R. K. Brayton, Preventing
OBDD Blow-ups via Domain Transformations Guided by High-Level Specifications,
International Workshop on Logic Synthesis (IWLS), Tahoe City, CA Workshop Notes
Volume 2, 317-333, February 1998.
134. E. Goldberg, T. Villa, R. Brayton, A.
Sangiovanni-Vincentelli, A Fast and Robust Exact Algorithm for Face
Embedding, IEEE/ACM International Conference on CAD, ICCAD 97, pp. 296-303,
November 1997.
135. E. Goldberg, L. Carloni, T.
Villa, R. Brayton, A. Sangiovanni-Vincentelli, Negative Thinking by
Incremental Problem Solving: Application to Unate Covering, IEEE/ACM
International Conference on CAD, ICCAD 97, pp. 91-97, November 1997.
136. T. Kam, T. Villa, R. K.
Brayton, and A. Sangiovanni-Vincentelli, Explicit and implicit algorithms
for binate covering problems, IEEE Trans. on CAD, vol.16, (no.7), July
1997. p.677-91
137. E. Goldberg, T. Villa, R.
Brayton, A. Sangiovanni-Vinceltenni, "Theory and Algorithms for Face
Hypercube Embedding", International Workshop on Logic Synthesis (IWLS),
May 1997.
138. E. Goldberg, L. Carloni,
T. Villa, R. Brayton, A. Sangiovanni-Vincentelli, "Negative Thinking in
Search Methods; Application to Unate Covering, International Workshop on Logic
Synthesis (IWLS), May 1997.
139. T. Kam, T. Villa, R.
Brayton, A. Sangiovanni-Vincentelli, Multi-valued decision diagrams: theory
and applications, International Journal on Multiple-Valued Logic Volume 4,
Numbers 1-2 (1998), pages 9-62.
140. E. Goldberg, T. Villa, R. Brayton, A. Sangiovanni-Vincentelli,
Theory and Algorithms for Face Hypercube Embedding, IEEE Trans. on CAD,
June 1998, vol.17, (no.6): 472-88.
141. L.P. Carloni, E. I.
Goldberg, T. Villa, R. K. Brayton, A. Sangiovanni-Vincentelli, Aura II:
Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems,
VLSI: Integrated Systems on Silicon: (P. Ivey and J. Marques-Silva editors),
Kluwer 1999.
142. Carloni, L.P.; Goldberg, E.I.; Villa, T.; Brayton, R.K. AURA
II: combining negative thinking and branch-and-bound in unate covering problems
VLSI: Systems on a Chip. IFIP TC10 WG10.5 Tenth International Conference on
Very Large Scale Integration (VLSI'99)
143. E. I. Goldberg, L. P. Carloni,
T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Negative
Thinking in Branch-and-Bound: The Case of Unate Covering, IEEE Trans. on
CAD, March 2000, vol. 19, (no. 3): 281-294.
144. Evgueni Goldberg, Mukul R Prasad, Robert K Brayton Using
Problem Symmetry in Search Based Satisfiability Algorithms in Proceedings
of the Design Automation & Test in Europe Conference (DATE 2002), pp.
134-141, March 2002, Paris, France. best
paper
4.1.5 Technology Mapping and FPGA Synthesis
(1980 – 2000)
145. R.K. Brayton and R.H.
Risch ,”Combinational Logic Design Using Cascode Current Switch”, ICCC Proceedings, Rye, NY, October 1980.
146. R.K. Brayton, C.L. Chen,
R.H.J.M. Otten and Y.Y. Yamour , “An SCVS/Domino Silicon Compiler for Automated
Macro Design”, IBM Technical Memo, 1984.
147. R.K. Brayton, C.L. Chen,
C.T. McMullen, R.H.J.M. Otten and Y.Y. Yamour , “Automatic Implementation of
Switching Functions as Dynamic CMOS Circuits”, CICC, May 1984; Digital VLSI
Systems, Ed. M.I. Elmasry, IEEE Press, pp. 225-229, 1985.
148. C. Moon, B. Lin and R.K.
Brayton, “Technology Mapping for Sequential Logic Synthesis”, International
Workshop on Logic Synthesis, May 1989.
149. R. Murgai, Y. Nishizaki,
N. Shenoy, R. Brayton and A. Sangiovanni-Vincentelli, Logic Synthesis for
Programmable Gate Arrays, Proc. of 1990 27th ACM/IEEE Design Automation
Conference, pp. 620-625, June 1990.
150. A. Malik, D. Harrison, and
R. Brayton, “Three-Level Decomposition with Application to PLDs”, Proc. of IEEE
International Conference on Computer Design, October 1991.
151. R. Murgai, R. K. Brayton,
N. Shenoy and A. Sangiovanni-Vincentelli, Improved Logic Synthesis Algorithms
for Table Look-Up Architectures, Proc. of ICCAD-91, pp. 564-567, November 1991.
152. R. Murgai, R. K. Brayton
and A. Sangiovanni-Vincentelli, "On the Complexity of Boolean Functions
for Table Look Up Architectures," 2nd International Workshop on Field
Programmable Logic and Applications, Vienna, Austria, September 1992.
153. R. Murgai, R. K. Brayton
and A. Sangiovanni-Vincentelli, "An Improved Synthesis Algorithm for
Multiplexor-based PGA's," Proceedings of the 29th Design Automation
Conference pp. 380-387, 1992.
154. H. Savoj, M. J. Silva, R.
K. Brayton and A. Sangiovanni-Vincentelli, "Boolean Matching in Logic
Synthesis," Proceedings of the European Design Automation Conference -
EURO DAC - EURO VHDL, pp. 168- 177.
155. P. R. Stephan and R. K.
Brayton, "A Synthesis and Verification Criterion for Logic Gate
Models," IWLS, May 1993.
156. P. R. Stephan and R. K.
Brayton, "Physically Realizable Gate Models," UC Berkeley ERL Memo
UCB/ERL M93/33, May 1993.
157. R. Murgai, R.K. Brayton and
A. Sangiovanni-Vincentelli , “Some Results on the Complexity of Boolean
Functions for Table Look Up Architectures”, Proceedings of the International
Conference on Computer Design, October 1993 and submitted to the Journal of
VLSI Design 1993.
158. R. Murgai, R.K. Brayton
and A. Sangiovanni-Vincentelli, “Logic Synthesis for Field-Programmable Gate
Arrays”, Kluwer Academic Publishers, July 1995. Book
159. M. Prasad, D.
Kirkpatrick, R. Brayton, A. Sangiovanni-Vincentelli, "Domino Logic
Synthesis and Technology Mapping", International Workshop on Logic
Synthesis (IWLS), May 1997.
160. D. Jongeneel, R. Otten, Y.
Watanabe, R. K. Brayton, Area and Search Space Control for Technology
Mapping, Proceedings 2000 Design Automation Conference, 37th
DAC, 86-91, Los Angeles, CA June 2000
4.1.6 Delay Optimization (1988 – 1994)
161. R. Brayton, A.
Sangiovanni-Vincentelli, K. Singh and A. Wang, Timing Optimization of
Combinational Logic, Proc. 1988 Int. Conference. on CAD, pp. 282-285, November
1988.
162. H.J. Touati, Ch.W. Moon
and R. K. Brayton , “Performance-Oriented Technology Mapping” Proceedings of
MIT VLSI Conference, 1990.
163. A. Saldanha, R.K. Brayton
and A. Sangiovanni-Vincentelli, Redundancy and Delay in Logic Optimization, In
the Extended Abstract Vol. of TECHCON'90, San Jose, CA., October 1990.
164. S. Malik, K. J. Singh, R.
K. Brayton and A. Sangiovanni-Vincentelli, Performance Optimization of
Pipelined Circuits, Proc. of ICCAD-90, pp. 410-413, November 1990.
165. A. Saldanha, R. K.
Brayton and A. Sangiovanni-Vincentelli, Timing Optimization with Testability
Considerations, Proc. of ICCAD-90, pp. 460-463, November 1990.
166. H. Touati, H. Savoj and
R.K. Brayton, Delay Optimization of Combinational Logic Circuits through
Clustering and Partial Collapsing, 1991 International Workshop on Logic
Synthesis April 1991.
167. R. Murgai, R. K. Brayton
and A. Sangiovanni-Vincentelli, On Clustering for Minimum Delay/Area, Proc. of
ICCAD-91, pp. 6-9, November 1991.
168. N. Shenoy, R. K. Brayton,
R. Murgai and A. Sangiovanni-Vincentelli, Performance Directed Synthesis for
Table Look-Up Programmable Gate Arrays, Proc. of ICCAD-91, pp. 572-575,
November 1991.
169. P.McGeer, R.K. Brayton,
A. Sangiovanni-Vincentelli and S. Sahni, Performance Enhancement Through the
Generalized Bypass Transform, International Workshop on Logic Synthesis, 1991
and International Conference on Computer-Aided Design, 1991.
170. A. Saldanha and R. K.
Brayton," Optimizing Logic for Speed Size and Testability," Keynote
Address at CompEuro'92 IEEE International Conference on Computer Systems and
Software Engineering, The Hague, May 4, 1992. Chapter in book Computer Systems
and Software Engineering Kluwer Academic Press, May 1992, eds. P. Dewilde and
J. Vandewalle.
171. A. Saldanha, R.K. Brayton
and A. Sangiovanni-Vincentelli , “Circuit Structure Relations to Redundancy and
Delay”, IEEE Transactions on Computer-Aided Design, to appear 1994.