- J. M. Rabaey, A. Chandrakasan, B. Nikolic,
*Digital Integarted Circuits: A Design Perspective*, 2^{nd}edition, Prentice-Hall, 2003.

- D. Marković, R.W. Brodersen, B. Nikolić, “Circuit optimization,” in
*DSP Architecture Design Essentials*, D. Marković, R.W. Brodersen, Springer 2012. - D. Marković, R.W. Brodersen, B. Nikolić, “Architectural techniques,” in
*DSP Architecture Design Essentials*, D. Marković, R.W. Brodersen, Springer 2012. - D. Marković, R.W. Brodersen, B. Nikolić, “Digital filters,” in
*DSP Architecture Design Essentials*, D. Marković, R.W. Brodersen, Springer 2012. - D. Marković, R.W. Brodersen, B. Nikolić, C.-H. Yang, “MHz-rate multi-antenna decoders: Dedicated SVD chip example,” in
*DSP Architecture Design Essentials*, D. Marković, R.W. Brodersen, Springer 2012. - R. Winoto, B. Nikolić, “Discrete-time processing of RF signals,” in Advanced Techniques for Multi-Mode/Multi-Band RF Transceivers, G. Hueber and B. Staszewski, (eds.) Springer, 2009.
- L.-T. Pang, B. Nikolić, “Variability in deeply-scaled CMOS,” in Circuits at the Nanoscale: Communications, Imaging and Sensing, K. Iniewski, (ed.), CRC Press, 2008, pp. 25-37.
- B. Nikolic, M. Leung, E. Yeo, K. Fukahori, "Read/Write Channel Implementation,"
in
*Coding and Signal Processing for Recording*, B. Vasic, E. Kurtas (eds.) pp. 34-1 - 34-34, CRC Press, 2004. - . Kuusilinna, C. Chang, H.-M. Bluethgen, W. R. Davis, B. Richards, B. Nikolic,
R. W. Brodersen, "Real Time System-on-a-Chip Emulation," in
*Winning the SoC Revolution*by H. Chang, G. Martin, Norwell, MA: Kluwer Academic Publishers, 2003. pp. 229-253. - D. Chinnery, B. Nikolic, K. Keutzer, "Achieving 550MHz in a Standard Cell ASIC
Methodology," in
*Bridging the Gap Between ASIC and Custom: Tools and Techniques for High-Performance ASIC Design,*D. Chinnery, K. Keutzer, Norwell, MA: Kluwer Academic Publishers, 2002, pp. 345-360.

- C. Wu, E. Alon, B. Nikolić, “A wideband 400 MHz-to-4 GHz direct RF-to-digital multimode DS receiver,” to appear in
*IEEE Journal of Solid-State Circuits*, August 2014. - R. Jevtić, H.-P. Le, M. Blagojević, S. Bailey, K. Asanović, E. Alon, B. Nikolić, “Per-core DVFS with switched-capacitor converters for energy efficiency in manycore processors,” to appear in
*IEEE Transactions on Very-Large Scale Integration (VLSI) Design*, 2014. - D. Stepanović, B. Nikolić “A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS,”
*IEEE Journal of Solid-State Circuits*, vol.48, no.4, pp. 971-982, April 2013. - V. Nagpal, I-H. Wang, M. Jorgovanovic, D. Tse, B. Nikolić, “Coding and system design for quantize-map-and-forward relaying,”
*IEEE Journal of Selected Areas in Communications*, vol. 31, no.8, pp. 1423-1435, August 2013. - B. Zimmer, S. O. Toh, H. Vo, Y. Lee, O. Thomas, K. Asanovic, B. Nikolic, “SRAM assist techniques for operation in a wide voltage range in 28nm CMOS,”
*IEEE Transactions on Circuits and Systems-II: Express Briefs,*vol.59,no.12, pp. 853-857*,*Dec*.*2012. - S. Hoyos, C. W. Tsang, J. Vanderhaegen, Y. Chiu, Y. Aibara, H. Khorramabadi, B. Nikolić, “A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 split-control, fast coarse locking digital DLL in 0.13µm CMOS,”
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol. 20, no. 3, pp. 5464-568, March 2012. - J. Jeon. L. Hutin, R. Jevtic, N. Liu, Y. Chen, R. Nathanael, W. Kwon. M. Spencer, E. Alon, B. Nikolic, T.-J. K. Liu, “Multiple-input relay design for more compact implementation of digital logic circuits,”
*IEEE Electron Device Letters*, vol. 33, no. 2, pp. 281-283, Feb. 2012. - J.-H. Park, B. Richards, B. Nikolić, “A 2 Gb/s 5.6 mW digital LOS/NLOS equalizer for the 60 GHz band,”
*IEEE Journal of Solid-State Circuits*, vol.46, no.11, pp. 22524-2534, November 2011. - S.O. Toh, Z. Guo, T.-J. King Liu, B. Nikolić, “Characterization of dynamic SRAM stability in 45 nm CMOS,”
*IEEE Journal of Solid-State Circuits*, vol.46, no.11, pp. 2702-2712, November 2011. - B. Nikolić, J.-H. Park, J. Kwak, B. Giraud, Z. Guo, L.-T. Pang, S. O. Toh, R. Jevtić, K. Qian, C. Spanos, “Technology variability from a design perspective,”
*IEEE Transactions on Circuits and Systems-I: Regular Papers*, vol.58, no.9, pp.1996-2009, September 2011. - C. Shin, C. H. Tsai, M. H. Wub, C. F. Chang, Y. R. Liu, C. Y. Kao, G. S. Lin, K. L. Chiu, C.-S. Fu, C.-t. Tsai, C. W. Liang, B Nikolić, T.-J. King Liu, “Quasi-planar bulk CMOS technology for improved SRAM scalability,”
*Solid-State Electronics*, vol.65-66, pp.184-190, November-December 2011. - C. Shin, N. Damrongplasit, X. Sun, Y. Tsukamoto, B. Nikolić, T.-J. King Liu “Performance and yield benefits of quasi-planar bulk CMOS technology for 6-T SRAM at the 22 nm node,”
*IEEE Transactions on Electron Devices*, vol. 58, no. 7, pp. 1846-1854, July 2011. - S. Vamvakos, V. Stojanović, B. Nikolić, “Discrete-time, linear periodically time-variant phase-locked loop model for jitter analysis,”
*IEEE Transactions on Circuits and Systems-I: Regular Papers*, vol.58, no.6, pp.1211-1224, June 2011. - C. Shin, M. H. Cho, Y. Tsukamoto, B.-Y. Nguyen, C. Mazuré, B. Nikolić, T.-J. King Liu, “Performance and area scaling benefits of FD-SOI technology, for 6-T SRAM cells at the 22 nm node,”
*IEEE Transactions on Electron Devices*, vol. 57, no.6, pp.1301-1309, June 2010. - A. Carlson, Z. Guo, S. Balasubramanian, R. Zlatanovici, T.-J. King Liu, B. Nikolić, “SRAM read / write margin enhancements using FinFETs,”
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol. 18, no.6, pp. 887-900, June 2010. - Z. Zhang, V. Anantharam, M. J. Wainwright, B. Nikolić, “An efficient 10GBASE-T Ethernet LDPC decoder design with low error floors,”
*IEEE Journal of Solid-State Circuits*, vol. 45, no.4, pp. 843-855, April 2010. - L. Dolecek, Z. Zhang, V. Anantharam, M. Wainwright, B. Nikolić, “Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes,”
*IEEE Transactions on Information Theory*, vol.56, no.1 pp. 181-201, January 2010. - Z. Zhang, L. Dolecek, B. Nikolić, V. Anantharam, M. J. Wainwright, “Design of LDPC decoders for improved low error rate performance: Quantization and algorithm choices,”
*IEEE Transactions on Communications*, vol. 8, no. 11, pp. 3258-3268, November 2009. - Z. Guo, A. Carlson, L.-T. Pang, K. Duong, T.-J. King Liu, B. Nikolić, “Large-scale SRAM variability characterization in 45nm CMOS,”
*IEEE Journal of Solid-State Circuits*, vol. 44, no.11, pp. 3174-3192, Nov. 2009. - L. Dolecek, P. Lee, Z. Zhang, V. Anantharam, B. Nikolić, M. J. Wainwright, “Predicting error floors of structured LDPC codes: Deterministic bounds and estimates,”
*IEEE Journal of Selected Areas in Communications*, vol. 27, no. 6, pp. 908-917, September 2009. - L.-T. Pang, K. Qian, C. Spanos, B. Nikolić, “Measurement and analysis of variability in 45nm strained-Si CMOS technology,”
*IEEE Journal of Solid-State Circuits*, vol. 44, no. 8, pp. 2233-2244, August 2009. - L.-T. Pang, B. Nikolić, “Measurements and analysis of process variability in 90nm CMOS,”
*IEEE Journal of Solid-State Circuits*, vol.44, no.5, pp. 1655-1663, May 2009. - R. Zlatanovici, S. Kao, B. Nikolić, “Energy – delay optimization of 64-bit carry-lookahead adders with a 240ps 90nm CMOS design example,”
*IEEE Journal of Solid-State Circuits*, vol. 44, no.2, pp.569-583, February 2009. - B. Nikolić, “Design in the power-limited scaling regime,”
*IEEE Transactions on Electron Devices*, vol. 55, no. 1, pp. 71-83, January, 2008. (invited) - D. Markovic, B. Nikolic, R.W. Brodersen, "Power and Area Minimization for Multidimensional Signal Processing,"
*IEEE Journal of Solid-State Circuits*, vol. 42, no. 4, pp. 922-934, April 2007. - H.-I. Liu, V. Dai, A. Zakhor, and B. Nikolic, "Reduced Complexity Compression Algorithms for Direct-Write Maskless
Lithography Systems,"
*Journal of Microlithography, MEMS and MOEMS*, vol.6, no.1, pp. 013007-1 – 013007-12, Jan.-Mar. 2007. - J.M. Rabaey,
F. De Bernardinis, A. Niknejad, B. Nikolic, A. Sangiovanni-Vincentelli,
"Embedding Mixed-Signal Design in Systems-on-a-Chip,"
*Proceedings of the IEEE*, vol. 94, no. 6, pp. 1070-1088, June 2006.

- R. Zlatanovici, B. Nikolic, "Power-Performance Optimization for Custom Digital
Circuits,"
*Journal of Low Power Electronics*, vol. 2, no. 1, pp. 113-120, April 2006. - Y. Chiu, P.R. Gray, B. Nikolic, "A 14-bit, 12-MS/s CMOS Pipeline
ADC with over 100-dB SFDR,"
*IEEE Journal of Solid-State Circuits*vol. 39, no. 12, pp. 2139-2151, December 2004. - D. Markovic, V. Stojanovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen, "Methods for True Energy-Performance Optimization,"
*IEEE Journal of Solid-State Circuits*, vol. 39, no. 8, pp. 1282-1293, August 2004. - Y. Shimazaki, R. Zlatanovici, B. Nikolic, "A Shared-Well Dual-Supply-Voltage
64-bit ALU,"
*IEEE Journal of Solid-State Circuits*, vol. 39, no. 3, pp. 494-500, March 2004. - F. Ishihara, F. Sheikh, B. Nikolic, "Level-Conversion for Dual-Supply Systems,"
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol. 12, no.2, pp. 185-195, February 2004. - Y. Chiu, C. Tsang, B. Nikolic, P.R. Gray, "Least-Mean-Square Adaptive Digital
Background Calibration of Pipelined A/D Converters,"
*IEEE Transactions on Circuits and Systems, part I: Fundamental Theory and Applications*, vol. 51, no. 1, pp. 38-46, January 2004. - R. Lynch, E. Kurtas, A. Kuznetsov, E. Yeo, B. Nikolic, "The Search for a Practical
Iterative Detector for Magnetic Recording,"
*IEEE Transactions on Magnetics*, vol. 40, no. 1, pp. 213-218, January 2004. - E. Yeo, B. Nikolic, V. Anantharam, "Iterative Decoder
Architectures,"
*IEEE Communications Magazine*, vol. 41, no.8, pp. 132-140, August 2003. - E. Yeo, S. Augsburger, W.R. Davis, B. Nikolic, "A 500Mb/s Soft-Output Viterbi
Decoder,"
*IEEE Journal of Solid-State Circuits*, vol. 38, no. 7, pp. 1234-1241, July 2003. - W.R. Davis, N. Zhang, K. Camera, D. Markovic, T. Smilkstein, M.J.
Ammer, E. Yeo, S. Augsburger, B. Nikolic, R.W. Brodersen, "A Design
Environment for High Throughput, Low Power Dedicated Signal Processing
Systems,"
*IEEE Journal of Solid-State Circuits*, vol.37, no.3, pp. 420-431, March 2002. - B. Nikolic, M. Leung, L. Fu,
"Rate 8/9 Distance-Enhancing Code with Stationary Detector,"
*IEEE Transactions on Magnetics*, vol.37, no.3, pp. 1168-1174, May 2001. - M. Leung, B. Nikolic, L. Fu, T. Jeon,
"Reduced Complexity Sequence Detection for Higher Order Partial Response Channels",
*IEEE Journal of Selected Areas in Communications*, vol.19, no.4, pp.649-661, April 2001. - E. Yeo, P. Pakzad, B. Nikolic, V. Anantharam,
"VLSI Architectures for Iterative Decoders in Magnetic Recording Channels,"
*IEEE Transactions on Magnetics*, vol.37, no.2, pp.748-755, March 2001. - D. Markovic, B. Nikolic, V.G. Oklobdzija,
"A General Method in Synthesis of Pass-Transistor Circuits,"
*Microelectronics Journal*, vol. 31, no. 11-12, pp. 991-998, November 2000. - D. Maksimovic, V. Oklobdzija, B. Nikolic, K.W. Current, "Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply
,"
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol.8, no.4, pp. 460-463, August, 2000. - B. Nikolic, V. Stojanovic, V.G. Oklobdzija, W. Jia, J. Chiu, M. Leung,"Improved Sense Amplifier-Based Flip-Flop: Design and Measurements,"
*IEEE Journal of Solid State Circuits*, vol. 35, no.6, pp.876-884, June 2000. - B. Nikolic, D.V. Tosic, S. Marjanovic, "Symbolic Analysis of Feedback
Amplifier Circuits," (in Serbo-Croat),
*Tehnika: Elektrotehnika*, Vol. 45, No 7-8, pp. E1-E5, July/August 1996.

- M. Weiner, M. Jorgovanovic, A. Sahai, B. Nikolić, “Design of a low-latency, high-reliability wireless communication system for control applications,” to be presented at the
*IEEE International Conference on Communications, ICC’14*, Sydney, Australia, June 10-14, 2014. - X. Xiao, B. Nikolić, “A dual-mode, correlation-based spectrum sensing receiver for TV white space applications achieving -104dBm sensitivity,” to be presented at the
*IEEE Radio-Frequency Integrated Circuits Symposium*,*RFIC’14,*Tampa Bay, FL, June 1-3, 2014. - B. Nikolić, M. Blagojević, O. Thomas, P. Flatresse, A. Vladimirescu, “Circuit design in nanoscale FDSOI technologies,” to be presented at the
*29th International Conference on Microelectronics, MIEL’14*, Belgrade, Serbia, May 12-15, 2014. (invited keynote) - M. Weiner, M. Blagojevic, S. Skotnikov, A. Burg, P. Flatresse, B. Nikolić, “A scalable 1.5 to 6Gb/s, 6.2 to 38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI,”
*2014 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC’14*, San Francisco, CA, February 2014, pp. 464-465. - C. Wu, B. Nikolić, “A 0.4 GHz - 4 GHz direct RF-to-digital ΣΔ multi-mode receiver,”
*Proc.**2013 European Solid-State Circuits Conference, ESSCIRC’2013*, Bucharest, Romania, September 16-20, 2013. pp. 275-278. - M. Jorgovanović, M. Weiner, I. -H. Wang, V. Nagpal, D. Tse and B. Nikolić, “Relay scheduling and interference cancellation for quantize-map-and-forward cooperative relaying,”
*Proc.**IEEE International Symposium on Information Theory, ISIT’13*, Istanbul, Turkey, July 7-12, 2013, pp. 1959-1963. - O. Thomas, B. Zimmer, B. Pelloux-Prayer, N. Planes, K-C. Akyel, L. Ciampolini, P. Flatresse, B. Nikolić, “6T SRAM design for wide voltage range in 28nm FDSOI,”
*Proc.**2012 IEEE International SOI Conference*, Napa, CA, October 1-4, 2012. p.6.3. (Best paper award) - D. Stepanović, B. Nikolić, “A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS,”
*2012 Symposium on VLSI Circuits*,*Digest of Technical Papers,*Honolulu, HI, June 13-15, 2012. pp.84-85. - B. Pelloux-Prayer, M. Blagojevic, O. Thomas, A. Amara, A. Vladimirescu, B. Nikolic, G. Cesana, P. Flatresse, “Planar fully depleted SOI technology: The convergence of high performance and low power towards multimedia mobile applications,”
*2012 IEEE Faible Tension Faible Consommation, 11th Low Voltage Low Power Conference, IEEE FTFC*, Paris France, June 6-8, 2012. - B. Nikolić, “Managing variability for ultimate energy efficiency,”
*Proc.**European Conference on Circuit Theory and Design*, Linkoping, Sweden, August 29-31, 2011, pp. 1-4 (keynote) - S.O. Toh, T.-J. King Liu, B. Nikolić, “Impact of random telegraph signaling noise on SRAM stability,”
*2011 Symposium on VLSI Technology*,*Digest of Technical Papers*, Kyoto, Japan, June 14-16, 2011, pp. 204-205. - M. Weiner, Z. Zhang, B. Nikolić, “LDPC decoder architecture for high-data rate personal-area networks, “
*Proc.**2011 IEEE International Symposium on Circuits and Systems, ISCAS’2011*, May 15-18, 2011, Rio de Janeiro, Brazil, pp. 1784-1787. - J.-H. Park, B. Richards, B. Nikolić, “A 2-Gb/S 5.6-mW digital equalizer for a LOS/NLOS receiver in the 60GHz band,"
*Proc.**2010 IEEE Asian Solid-State Circuits Conference*, Beijing, China, November 8-10, 2010. P. 12-7. - V. Nagpal, I.-H.Wang, M. Jorgovanović, D. Tse, B. Nikolić, “Quantize-map-and-forward relaying: Coding and system design,”
*Proc.**48th Annual Allerton Conference on Communication, Control and Computing*, Monticello, IL, September 28-October 1, 2010. Pp. 443-450. - B. Nikolić, B. Giraud, Z. Guo, L.-T. Pang, J-H. Park, S. O. Toh, “Technology variability from a design perspective,” in
*Proc.**IEEE Custom Integrated Circuits Conference, CICC’10*, San Jose, CA, September 19-22, 2010. (invited) - L. T.-N. Wang, N. Xu, S.-O. Toh, A. R. Neureuther, T.-J. King Liu, B. Nikolić, “Parameter-specific ring oscillator for process monitoring at the 45 nm node,”
*Proc.**IEEE Custom Integrated Circuits Conference, CICC’10*, San Jose, CA, September 19-22, 2010. - C. Shin, B. Nikolić, T.-J. King Liu, C. H. Tsai, M. H. Wu, C. F. Chang, Y. R. Liu, C. Y. Kao, G. S. Lin, K. L. Chiu, C.-S. Fu, C.-t. Tsai, C. W. Liang, “Tri-gate bulk CMOS technology for improved SRAM scalability,”
*Proc.**40th European Solid-State Device Research Conference, ESSDERC’2010*, Sevilla, Spain, September 13-17, 2010.pp 142-145. - S.O. Toh, Z. Guo, B. Nikolić, “Dynamic SRAM stability characterization in 45nm CMOS,”
*2010 Symposium on VLSI Circuits*,*Digest of Technical Papers,*Honolulu, HI, June 16-18, 2010, pp. 35-36. - F. Sheikh, M. Miller, B. Richards, D. Marković, B. Nikolić, “A 1–190Msample/s 8–64 tap energy-efficient reconfigurable FIR filter for multi-mode wireless communication,”
*2010 Symposium on VLSI Circuits*,*Digest of Technical Papers, Honolulu*, HI, June 16-18, 2010, pp. 207-208. - B. Nikolić, C. Shin, M. H. Cho, X. Sun, T.-J. King Liu, B.-Y. Nguyen, “SRAM design in fully-depleted SOI technology,”
*Proc.**2010 IEEE International Symposium on Circuits and Systems, ISCAS’2010*, May 30-June 2, 2010, Paris, France. - Y. Tsukamoto, S. O. Toh, C. Shin, A. Mairena, T.-J. King Liu, B. Nikolić, “Analysis of the relationship between random telegraph signal and negative bias temperature instability,”
*Proc.*2010*IEEE International Reliability Physics Symposium*, Anaheim, CA, May 2-6, 2010, pp. 1117-1121. - C. H. Tsai, T.-J. King Liu, S. H. Tsai, C. F. Chang, Y. M. Tseng, R. Liao, R. M. Huang, P. W. Liu, C. T. Tsai, C. Shin, B. Nikolić and C. W. Liang, “Segmented tri-gate bulk CMOS technology for device variability improvement,”
*Proc.**2010 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)*, Hsinchu, Taiwan, April 26-28, 2010, pp. 114-115. - H.-I Liu, B. Richards, A. Zakhor, B. Nikolić, “Hardware implementation of Block GC3 lossless compression algorithm for direct-write lithography systems,”
*Proc.**SPIE Advanced Lithography*, vol. 7637, San Jose, CA, Feb. 21-25, 2010, pp. 763716-1 - 763716-11. - J. Tsai, S.O. Toh, Z. Guo, L.-T.Pang, T.-J. King, B. Nikolić, “SRAM variability characterization using tunable ring oscillators in 45nm CMOS,”
*2010 IEEE International Solid-State Circuits Conference*,*Digest of Technical Papers,*San Francisco, CA, February 7-10, 2010, pp. 354-355. - S.O. Toh, Y. Tsukamoto, Z. Guo, L. Jones, T.-J. King Liu, B. Nikolić, “Impact of random telegraph signals on Vmin in 45nm SRAM,”
*2009 IEEE International Electron Devices Meeting, IEDM’09*,*Technical Digest,*Baltimore, MD, December 7-9, 2009, pp. 767-770. - Z. Zhang, L. Dolecek, P. Lee, V. Anantharam, M. J. Wainwright, B. Richards, B. Nikolić, “Low error rate LDPC decoders,”
*Forty-Third Asilomar Conference on Signals, Systems and Computers*,*2009 Conference Record*, Pacific Grove, CA, Nov. 1-4, 2009. pp. 1278-1282. (invited) - T.-J. King Liu, C. Shin, M. H. Cho, X. Sun, B. Nikolić, B.-Y. Nguyen, “SRAM cell design considerations for SOI technology,”
*Proc. 2009 IEEE SOI Conference*, Foster City, CA, October 5-8, 2009, p.3.1. (invited). - C. Shin, M. H. Cho, Y. Tsukamoto, B.-Y. Nguyen, B. Nikolić, T.-J. King Liu, “SRAM yield enhancement with thin-BOX FD-SOI,”
*Proc. 2009 IEEE SOI Conference*, Foster City, CA, October 5-8, 2009. p. 3.5. (Best paper award and best student paper award) - S.D. Vamvakos, V. Stojanović, B. Nikolić, “Discrete-time, cyclostationary phase-locked loop model for jitter analysis,”
*Proc. 2009 IEEE Custom Integrated Circuits Conference*, San Jose, CA, September 13-16, 2009, pp. 637-640. - J.-H. Park, L.-T. Pang, K. Duong, B. Nikolić, “Fixed- and variable-length ring oscillators for variability characterization in 45nm CMOS,”
*Proc. 2009 IEEE Custom Integrated Circuits Conference*, San Jose, CA, September 13-16, 2009, pp. 519-522. - B. Richards, N. Nicolici, H. Chen, K. Chao, R. Abiad, D. Werthimer, B. Nikolić, “A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications,”
*Proc. 2009 IEEE Custom Integrated Circuits Conference*, San Jose, CA, September 13-16, 2009, pp. 499-502. - V. Nagpal, S. Pawar, D. Tse, B. Nikolić, “Cooperative multiplexing in the multiple antenna half duplex relay channel,”
*Proc. 2009 IEEE International Symposium on Information Theory*, Seoul, Korea, June 28 – July 3, 2009, pp. 1438-1442. - Z. Zhang, V. Anantharam, M. J. Wainwright, B. Nikolić, “A 47 Gb/s LDPC decoder with improved low error rate performance,”
*2009 Symposium on VLSI Circuits, Digest of Technical Papers*, Kyoto, Japan, June 16-18, 2009. pp. 286-287. - R. Winoto, B. Nikolić, “A highly reconfigurable 400-1700MHz receiver using a down-converting sigma-delta A/D with a 59-dB SNR, and 57-dB SFDR over 4-MHz bandwidth,”
*2009 Symposium on VLSI Circuits*,*Digest of Technical Papers*, Kyoto, Japan, June 16-18, 2009. pp. 142-143. - K. Qian, B. Nikolić, C. Spanos, “Hierarchical modeling of spatial
variability with a 45nm example,”
*Proc. SPIE 7275*, San Jose, CA, February 22-27, 2009, pp. 727505-1-727505-12. - L. T.-N. Wang, L.-T. Pang, A. R. Neureuther, B. Nikolić, “Parameter-specific
electronic measurement and analysis of sources of variation using ring
oscillators,”
*Proc. SPIE 7275*, San Jose, CA, February 22-27, 2009, pp. 72750L-7275L-10. - Z. Zhang, L. Dolecek, B. Nikolić, V. Anantharam, M. J. Wainwright, “Lowering
LDPC error floors by postprocessing,”
*Proc. IEEE Globecom 2008*, New Orleans, LA, November 30 – December 4, 2008. - L.-T. Pang, B. Nikolić, “Measurement and analysis of variability in 45nm
strained-Si CMOS technology,”
*Proc. 2008 Custom Integrated Circuits Conference, CICC’2008*, San Jose, CA, September 21-24, 2008, pp. 129-132. - A. Carlson, Z. Guo, L.-T. Pang, T.-J. King Liu, B. Nikolić, “Compensation of
systematic variations through optimal biasing of SRAM wordlines,”
*Proc. 2008 Custom Integrated Circuits Conference, CICC’2008*, San Jose, CA, September 21-24, 2008, pp. 411-414. - C. Tsang, Y. Chiu, J. Vanderhaegen, S. Hoyos, C. Chen, R. Brodersen, B.
Nikolić, “Background ADC calibration in digital domain,”
*Proc. 2008 Custom Integrated Circuits Conference, CICC’2008*, San Jose, CA, September 21-24, 2008, pp. 301-304. - S. Hoyos, C. Tsang, J. Vanderhaegen, Y. Chiu, Y. Aibara, H. Khorramabadi, B.
Nikolić, “A 15 MHz – 600 MHz, 20 mW, 0.38mm2, Fast coarse locking digital DLL in
0.13m CMOS,”
*Proc. 34th European Solid-State Circuits Conference, ESSCIRC 2008*, Edinburgh, Scotland, September 15-19, 2008, pp. 90-93. - T. Oshima, T. Takahashi, T. Yamawaki, C. Tsang, D. Stepanovic, B. Nikolic,
“Fast nonlinear deterministic calibration of pipelined A/D converters,”
*Proc. 51st Midwest Symposium on Circuits and Systems, MWSCAS’2008*, August 10-13, 2008, pp. 914-917. - P. Lee, L. Dolecek, Z. Zhang, V. Anantharam, B. Nikolić, M. Wainwright,
“Error floors in LDPC codes: fast simulation, bounds and hardware emulation,”
*Proc.2008 IEEE International Symposium on Information Theory*, Toronto, ON, Canada, July 6-11, 2008, pp. 444-448. - Z. Guo, A. Carlson, L.-T. Pang, K. Duong, T.-J. King Liu, B. Nikolić,
“Large-scale read/write margin measurement in 45nm CMOS SRAM arrays,”
*2008 Symposium on VLSI Circuits, Dig. Tech Papers*, Honolulu, HI, June 18-20, 2008. pp. 42-43. - L. T.-N Wang, W.J. Poppe, L.-T. Pang, A.R. Neureuther, E. Alon, B. Nikolic,
“Hypersensitive parameter-identifying ring oscillators for lithography process
monitoring,”
*Proc. SPIE 6925*, Santa Clara, CA, February 2008, pp. 69250P-1 – 69250-10. - B. Nikolić, “Power-limited design,”
*Proc. 14th International Conference on Electronics, Circuits and Systems, ICECS’07*, Marrakech, Morocco, December 11-14, 2007, pp. 927-930. (invited) - B. Nikolić, “Towards efficient spectrum sharing,”
*Proc. Sixth IEEE Dallas Workshop on Circuits and Systems, DCAS’07*, Dallas, TX, November 2007, pp. 33-38. (invited) - Z. Zhang, R. Winoto, A. Bahai, B. Nikolic, "Peak-to-Average Power Ratio Reduction
in an FDM Broadcast System,"
*Proc. IEEE 2007 Workshop on Signal Processing Systems, SIPS 2007*, Shanghai, China, October 17-19, 2007. pp. 25-30. - Markovic, C. Chang, B. Richards, H. So, B. Nikolic, R.W. Brodersen, "
ASIC design and verification in an FPGA environment,"
*Proc. IEEE Custom Integrated Circuits Conference, CICC’07*, San Jose, CA, Sept. 16-19, 2007, pp. 737-740. - L. Dolecek, Z. Zhang, M. Wainwright, V. Anantharam, B. Nikolic, "Evaluation of the low frame error rate performance
of LDPC codes using importance sampling,"
*Proc. 2007 IEEE Information Theory Workshop, ITW’07*, Lake Tahoe, CA, Sept. 2-6, 2007. - Z. Zhang, L. Dolecek, M. Wainwright, V. Anantharam, B. Nikolic, "Quantization effects in low-density parity-check
decoders,"
*Proc. IEEE International Conference on Communications, ICC’07*, Glasgow, Scotland, June 24-27, 2007, pp. 6231-6237. - L. Dolecek, Z. Zhang, V. Anantharam, M. Wainwright, B. Nikolic, "Analysis
of absorbing sets for array-based LDPC codes,"
*Proc. IEEE International Conference on Communications, ICC’07*, Glasgow, Scotland, June 24-27, 2007, pp. 6261-6268. - Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, M. Wainwright, “Investigation
of error floors of structured low-density parity-check codes
by hardware emulation,"
*Proc. IEEE GLOBECOM 2006*, San Francisco, CA, November 27 – December 1, 2006. - D. Fang, R. Roberts, B. Nikolic, "A 6-b DAC and analog DRAM for a maskless lithography interface in 90nm CMOS," Proc. IEEE Asian Solid-State Circuits Conference, Hangzhou, China, November 13-15, 2006. pp. 423-426.
- A. Parsons, D. Backer, C. Chang, D. Chapman, H. Chen, P. Crescini, C. de Jesus, C. Dick, P. Droz, D. MacMahon, K. Meder,
J. Mock, V. Nagpal, B. Nikolic, A. Parsa, B. Richards, A. Siemion, J. Wawrzynek, D. Werthimer, M. Wright,
"PetaOp/Second FPGA Signal Processing for SETI and Radio Astronomy,"
*Proc. Asilomar Conference on Signals, Systems, and Computers*, Pacific Grove, CA, October 29-November 1, 2006. (invited). pp. 2031-2035. - F. Sheikh, M. Ler, R. Zlatanovici, D. Markovic, B. Nikolic, "
Power-performance optimal DSP architectures and ASIC
implementation,"
*Proc. Asilomar Conference on Signals, Systems, and Computers*, Pacific Grove, CA, October 29-November 1, 2006. pp. 1480-1485.(invited) - B. Nikolic, L.T. Pang, "Measurements and analysis of process variability in 90nm CMOS,
"
*Proc. 8th International Conference on Solid-State and Integrated Circuit Technology*, Shanghai, China, October 23-26, 2006. (invited), pp. 505-508. - A. Carlson, Z. Guo, S. Balasubramanian, L.-T. Pang, T.-J. King Liu, B. Nikolic, "
FinFET SRAM with enhanced
read/write margins,"
*Proc. IEEE International SOI Conference*, Niagara Falls, NY, October 2-5, 2006. pp. 105-106. - D. Markovic,
R.W. Brodersen, B. Nikolic, ”A 70GOPS, 34mW Multi-carrier MIMO chip in 3.5mm
^{2},"*2006 Symposium on VLSI Circuits, Digest of Technical Papers*, Honolulu, HI, June 15-17, 2006. pp. 196-197. - S. D.
Vamvakos, V. Stojanovic, J. L. Zerbe, C. W. Werner, D. Draper, B. Nikolic, "PLL
on-chip jitter measurement: Analysis and design,"
*2006 Symposium on VLSI Circuits, Digest of Technical Papers*, Honolulu, HI, June 15-17, 2006. pp. 90-91. - C.W. Tsang,
Y. Chiu, B. Nikolic, "1.2V, 10.8mW, 500kHz Sigma-delta modulator with 84dB
SNDR and 96dB SFDR,"
*2006 Symposium on VLSI Circuits, Digest of Technical Papers*, Honolulu, HI, June 15-17, 2006. pp. 202-203. - L.T. Pang, B.
Nikolic, "Impact of layout on 90nm CMOS
process parameter fluctuations,"
*2006 Symposium on VLSI Circuits, Digest of Technical Papers*, Honolulu, HI, June 15-17, 2006. pp. 84-85. - D. Markovic, B.Nikolic, R.W.Brodersen, "Power and area efficient
VLSI architectures for communications signal processing,"
*Proc. IEEE International Conference on Communications, ICC'2006*, Istanbul, Turkey, June 11-15, 2006. pp. 3323-3328. - H.-I. Liu, V.Dai, A. Zakhor, B. Nikolic, "Reduced complexity compression algorithms for direct-write maskless lithography systems," Proc. SPIE, vol. 6151, San Jose, CA, February 19-24, 2006, pp. 61512B-1-14.
- S. Kao, R.
Zlatanovici, B. Nikolic, "A 250ps 64-bit Carry-Lookahead
Adder in 90nm CMOS," 2006
*IEEE International Solid-State Circuits Conference*,*ISSCC’06*,*Digest of Technical Papers,*San Francisco, CA, February 4-8. 2006. pp. 438-439, 664. - E.Yeo, B.
Nikolic, "A 1.1-Gb/s 4092-bit low-density parity-check
decoder,"
*IEEE Asian Solid-State Circuits Conference*, Hsinchu, Taiwan, November 1-3, 2005. pp. 237-240. - R. Zlatanovici,
B. Nikolic, "Power-performance optimization for custom
digital circuits,"
*Proc. PATMOS’05, LNCS 3728*, Leuven, Belgium, September 20-23, 2005. pp. 404-414. - Y. Chiu,
B. Nikolic, P.R. Gray, "Scaling of
analog-to-digital converters into ultra-deep-submicron CMOS,"
*Proceedings, 2005 IEEE Custom Integrated Circuits Conference*, Sam Jose, CA, September 17-21, 2005, pp. 375-382. (invited). - Z. Guo, S.
Balasubramanian, R. Zlatanovici, T.-J. King, B. Nikolic,"FinFET-based SRAM design,"
*Design, ISLPED’05*, San Diego, CA, August 8-10, 2005, pp. 2-7. (Best paper award). - S. Balasubramanian, J. L. Garrett, V.
Vidya, B. Nikolic, T.-J. King, "Energy-Delay Optimization of Thin-Body MOSFETs
for the Sub-15 nm Regime,"
*Proc.**IEEE SOI Conference*2004, Charleston, SC, October 4-7, 2004. pp. 27-29. - E. Liao, E. Yeo, B. Nikolic, "Low-density parity-check code
constructions for hardware implementation,"
*Proceedings 2004 IEEE International Conference on Communications*, ICC'04, Paris, France, June 20-24, 2004, pp. 2573-2577. - S.D. Vamvakos, C. Werner, B. Nikolic, "Phase-locked loop
architecture for adaptive jitter optimization,"
*Proceedings of the 2004 IEEE International Symposium on Circuits and Systems (ISCAS'04)*, vol. IV, Vancouver, BC, Canada, May 23-26, 2004, pp. IV-161 - IV-164. - B. Nikolic, B. Wild, V. Dai, Y. Shroff, B. Warlick, A. Zakhor, W. Oldham,
"Layout decompression chip for maskless lithography,"
*Proc. of SPIE*, Vol. 5374, Santa Clara, CA, Feb. 24-26, 2004. - B. Warlick, B. Nikolic, "Mixed-signal data interface for maskless lithography,"
*Proc. of SPIE*, Vol. 5374, Santa Clara, CA, Feb. 24-26, 2004. - Y. Chiu, P.R. Gray, B. Nikolic, "
A 1.8-V, 14-b, 10-MS/s Pipelined ADC in 0.18-µm CMOS with 99-dB SFDR,"
*IEEE International Solid-State Circuits Conference, ISSCC'04*,*Digest of Technical Papers*, San Francisco, CA, February 14-19. 2004. pp. 458-459, 539. - R. Zlatanovici, B. Nikolic, "Power-Performance Optimal 64-bit
Carry-Lookahead Adders,"
*Proceedings of the 29*, September 16-18, 2003, Estoril, Portugal, pp. 321-324.^{th}European Solid-State Circuits Conference, ESSCIRC'03 - B. Nikolic, L. Chang, T.-J. King, "Performance of Deeply-Scaled,
Power-Constrained Circuits," 2003
*International Conference on Solid State Devices and Materials, SSDM 2003*, Tokyo, Japan, September 16-18, 2003, pp. 154-155. (invited). - F. Ishihara, F. Sheikh, B. Nikolic, "Level Conversion for Dual
Supply Systems,"
*Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'03*, Seoul, Korea, August 25-27, 2003. pp. 164-167. - R. Lynch, E. Kurtas, A. Kuznetsov, E. Yeo, B. Nikolic, "The Search
for a Practical Iterative Decoder for Magnetic Recording,"
*Digests of the 2003 Magnetic Recording Conference, TMRC'03*, Santa Clara, CA, August 18-20, 2003, p. B1. - C. Chang, K. Kuusilinna, B. Richards, A. Chen, N. Chan, R.W. Brodersen, B. Nikolic, "Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment, Proceedings 14th IEEE International Workshop on Rapid Systems Prototyping, San Diego, CA, June 9-11, 2003, pp. 148-154
- S. Balasubramanian, L. Chang, B. Nikolic, T.-J. King,
"Circuit-Performance Implications for Double-Gate MOSFET Scaling Below
25nm,"
*2003 Silicon Nanoelectronics Workshop*, Kyoto, Japan, June 8-9, 2003. - Y. Shimazaki, R. Zlatanovici, B. Nikolic, "A Shared-Well
Dual-Supply-Voltage 64-bit ALU," 2003
*IEEE International Solid-State Circuits Conference, ISSCC'03, Digest of Technical Papers*, San Francisco, CA, February 9-13, 2003, pp. 104-105, 481. - R.W. Brodersen, M.A. Horowitz, D. Markovic, B. Nikolic, V.
Stojanovic, "Methods for True Power Minimization,"
*International Conference on Computer-Aided Design, ICCAD-2002, Digest of Technical Papers*, San Jose, CA, November 10-14, 2002, pp. 35-42. (invited). - E. Yeo, S. Augsburger, W.R. Davis, B. Nikolic, "Implementation of
High-Throughput Soft-Output Viterbi Decoders,"
*IEEE Workshop on Signal Processing Systems, SIPS'02*, San Diego, CA, October 16-18, 2002. - V. Stojanovic, D. Markovic, B. Nikolic, M.A. Horowitz, R.W.
Brodersen, "Energy-Delay Tradeoffs in Combinational Logic using Gate
Sizing and Supply Voltage Optimization,"
*Proceedings of the 28*, Florence, Italy, September 24-26, 2002. pp. 211-214.^{th}European Solid-State Circuits Conference, ESSCIRC'2002 - E. Yeo, S. Augsburger, W.R. Davis, B. Nikolic, "A 500Mb/s
Soft-Output Viterbi Decoder,"
*Proceedings of the 28*, Florence, Italy, September 24-26, 2002. pp. 523-526.^{th}European Solid-State Circuits Conference, ESSCIRC'2002 - S. Augsburger, B. Nikolic, ""Reducing Power with Dual-Supply,
Dual-Thresholds and Transistor Sizing,"
*Proceedings IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD'02*, Freiburg, Germany, September 16-18, 2002. - E. Yeo, B. Nikolic, V. Anantharam, ""Architectures and
Implementation of Low-Density Parity-Check Decoding Algorithms,"
*45th IEEE Midwest Symposium on Circuits and Systems, MWSCAS 2002*, Tulsa OK, August 4-7, 2002. (invited). - E. Yeo, P. Pakzad, B. Nikolic, V. Anantharam, "High Throughput
Low-Density Parity-Check Decoder Architectures,"
*Proceedings 2001 Global Conference on Communications, Globecom'01*, San Antonio, TX, November 25-29, 2001. pp. 3019-3024. - D. Petrovic, B. Nikolic, K. Ramchandran, "List Viterbi Decoding
with Continuous Error Detection for Magnetic Recording Channels,"
*Proceedings 2001 Global Conference on Communications, Globecom'01*, San Antonio, TX, November 25-29, 2001. pp. 3007-3011. - W.R. Davis, N. Zhang, K. Camera, D. Markovic, T. Smilkstein, N.
Chan, M.J. Ammer, E. Yeo, B. Nikolic, R.W. Brodersen, "An Automated
Design Flow for Low-Power, High-Throughput Dedicated Signal Processing
Systems,"
*Thirty-Fifth Asilomar Conf. on Signals, Systems and Computers, Conf. Record*, vol. 1, Pacific Grove, CA, November 4-7, 2001. pp.475-480. - D. Markovic, B. Nikolic, R.W. Brodersen, "Analysis and Design of Low-Energy Flip-Flops,"
*Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design*, ISLPED'01, Huntington Beach, CA, August 6-7, 2001, pp.52-55. - D. Chinnery, B. Nikolic, K. Keutzer, "Achieving 550MHz in an ASIC Methodology,"
*Proceedings of the 38*, DAC'2001, Las Vegas, NV, June 18-22, 2001, pp. 420-425.^{th}Design Automation Conference - W.R. Davis, N. Zhang, K. Camera, F. Chen, D. Markovic, N. Chan, B. Nikolic, R.W. Brodersen,
"A Design Environment for High Throughput, Low Power, Dedicated Signal Processing Systems,"
*Proceedings of the IEEE Custom Integrated Circuits Conference,*CICC'2001, San Diego, CA, May 6-9, 2001. pp. 545-548. - J.L. da Silva, Jr, J. Shamberger, M.J. Ammer, C. Guo, S.-F. Li, R. Shah, T.Tuan, M. Sheets, J.M. Rabaey, B. Nikolic, A. Sangiovanni-Vincentelli, P. Wright, "Design Methodology for PicoRadio Networks,"
*Design, Automation and Test in Europe*,*DATE*'2001, Munich, Germany, March 13-16, 2001, pp.314-323. - E. Yeo, P. Pakzad, B. Nikolic, V. Anantharam, "VLSI Architectures for Iterative Decoders in Magnetic Recording Channels,"
*Digests of The Magnetic Recording Conference*,*TMRC*2000,*on Magnetic Recording Systems*, Santa Clara, CA, August 14-16, 2000, p. E6. - J. Popovic, B. Nikolic, K. W. Current, A. Pavasovic, D. Vasiljevic, "Low-Power CMOS RC Oscillators Based on Current Conveyors,"
*Proceedings of the*22^{nd}*IEEE International Conference on Microelectronics*,*MIEL*'2000, Nis, Yugoslavia, May 14-17, 2000, pp.691-694. - D. Markovic, B. Nikolic, V.G. Oklobdzija, "General Method in Synthesis of Pass-Transistor Circuits,"
*Proceedings of the*22^{nd}*IEEE International Conference on Microelectronics*,*MIEL*'2000, Nis, Yugoslavia, May 14-17, 2000, pp. 695-698. - B. Nikolic,
M. Leung, L. Fu, V.G. Oklobdzija, R. Yamasaki, "Reduced Complexity Sequence Detection for E
^{2}PR4 Magnetic Recording Channel," 1999.*IEEE Global Conference on Communications*,*GLOBECOM'99*,*Conference Record*, vol. 1, part B, Rio de Janeiro, Brazil, December 5-9, 1999, pp. 960-964. - B. Nikolic, V.G. Oklobdzija, "Design and optimization of sense amplifier-based flip-flops,"
*Proceedings of the 25*, Duisburg, Germany, September 21-23, 1999, pp. 410-413.^{th}European Solid-State Circuits Conference, ESSCIRC'99 - B. Nikolic, M. Leung, L.Fu, "A Rate 8/9 Sliding Block Code with Stataionary Detector for Magnetic Recording,"
*Proceedings*1999*International Conference on Communication*, ICC'99, vol. 3, Vancouver, BC, Canada, June 6-10, 1999, pp. 1653-1657. - B. Nikolic, V. Stojanovic, V.G. Oklobdzija, W. Jia, J. Chiu, M. Leung, "Sense Amplifier-Based Flip-Flop," 1999
*IEEE International Solid-State Circuits Conference, ISSCC*'99,*Digest of Technical Papers*, San Francisco, CA, February 15-17, 1999, pp. 282-283, 468. - J. Popovic, B. Nikolic, K. W. Current, A. Pavasovic, D. Vasiljevic, "CMOS Implementation of Low-power Oscillators Based on the Modified Fabre-Normand Current Conveyor,"
*Proceedings*1998.*International Conference on Electronics, Circuits and Systems, ICECS-98*, vol 2, Lisbon, Portugal, September 7-10, 1998, pp. 349-352. - B. Nikolic, S. Marjanovic, "A General Method of Feedback Amplifier Analysis,"
*Proceedings of the*1998*IEEE International Symposium on Circuits and Systems (ISCAS 98)*, vol. III, Monterey, CA, May 31 - June 3, 1998, pp. 415-418. - B.Nikolic, V.G. Oklobdzija, "Low Voltage BiCMOS TSPC Latch for High
Performance Digital Systems, "
*Proceedings of the*1998*IEEE International Symposium on Circuits and Systems (ISCAS'98)*, vol. II, Monterey, CA, May 31 - June 3, 1998, pp. 53-56. - D. Maksimovic, V. Oklobdzija, B. Nikolic, K.W. Current, "Clocked CMOS
Adiabatic Logic with Integrated Single-Phase Power-Clock Supply: Experimental
Results,"
*Proceedings 1997. International Symposium on Low-Power Electronics and Design*, Monterey, CA, August 18-20, 1997, pp. 323-327. Reprinted in*High-Performance System Design: Circuits and Logic*, IEEE Press 1999. - B. Nikolic, V. Oklobdzija, "A Single-Phase Clock High-Performance
BiCMOS Latch, "7
97, Singapore, Singapore, 10-12 September 1997.^{th}International Symposium on IC Technology, Systems, & Applications, ISIC- - D. Maksimovic, V. Oklobdzija, B. Nikolic, K.W. Current, "Design and
Experimental Verification of a CMOS Adiabatic Logic with Single-Phase
Power-Clock Supply,"
*Proceedings of the*40, Sacramento, CA, August 3-6, 1997, pp. 417-420.^{th}Midwest Symposium on Circuits and Systems - B. Nikolic, D.V. Tosic, S. Marjanovic, "Symbolic Analysis of Feedback
Amplifier Circuits",
*Proc.*4Leuven, Belgium, October 10-11, 1996, pp. 244-247.^{th}International Workshop on Symbolic Methods and Applications to Circuit Design, - B. Nikolic, B. Ristic, S. Marjanovic, "Data Transmission System Over
Electric Power Distribution Circuits," (in Serbo-Croat), II
*TELFOR Symposium*, Belgrade, Yugoslavia, 1994, pp. 258-261. - B. Ristic, B. Nikolic, S. Kovacevic, S. Marjanovic, "Data Transmission
Modem Over Electric Power Distribution Circuits," (in Serbo-Croat), XXXVIII
*ETRAN Conference*, Vol. II pp. Nis, Yugoslavia, 1994, pp. 79-80. - B. Nikolic, D. Vujadinovic, B. Ristic, S. Marjanovic, "Remote Power Meter Reading System," (in Serbo-Croat), XXXVIII
*ETRAN Conference*, Vol. II, Nis, Yugoslavia, 1994, pp. 77-78. - B. Nikolic, S. Kovacevic, B. Ristic, S. Marajanovic, "Power Distribution Circuits as a Communications Medium," (in Serbo-Croat), XXXVII
*ETAN Conference*, Vol. II - E, pp. 51-56, Belgrade, Yugoslavia, 1993, pp. 51-56.