Abstracting RTL Designs to the Term Level This page contains information on how to use v2ucl, the tool for abstracting Verilog to UCLID. To see a demo, first download the demo and the appropriate version of v2ucl below. For addition information on v2ucl, please refer to the tech report. 32-bit Linux binary: v2ucl 64-bit Linux binary: v2ucl Demo files: tgz Tech Report: here BV/Hybrid runtimes for varying flits/packet: eps pdf BV/Hybrid runtime and problem size ratios: eps pdf