Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley



MASIC Homepage  

EE W241A

Digital Integrated Circuits

CMOS devices and deep sub-micron manufacturing technology. CMOS inverters and complex gates. Modeling of interconnect wires. Optimization of designs with respect to a number of metrics: cost, reliability, performance, and power dissipation. Sequential circuits, timing considerations, and clocking approaches. Design of large system blocks, including arithmetic, interconnect, memories, and programmable logic arrays. Introduction to design methodologies, including laboratory experience.


Elad Alon, Associate Professor

He received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from Stanford University in 2001, 2002, and 2006, respectively. In Jan. 2007, he joined the University of California at Berkeley, where he is now an Associate Professor of Electrical Engineering and Computer Sciencesa as well as a co-director of the Berkeley Wireless Research Center (BWRC). He has held consulting or visiting positions at Xilinx, Sun Labs, Intel, AMD, Rambus, Hewlett Packard, and IBM Research, where he worked on digital, analog, and mixed-signal integrated circuits for computing, test and measurement, and high-speed communications. Dr. Alon received the IBM Faculty Award in 2008, the 2009 Hellman Family Faculty Fund Award, the 2010 UC Berkeley Electrical Engineering Outstanding Teaching Award, the 2010 ISSCC Jack Raper Award for Outstanding Technology Directions Paper, and the 2011 Symposium on VLSI Circuits Best Student Paper Award. His research focuses on energy-efficient integrated systems, including the circuit, device, communications, and optimization techniques used to design them.

Homepage: http://www.eecs.berkeley.edu/Faculty/Homepages/elad.html
Email:  elad@eecs

Jan Rabaey

Jan Rabaey, Professor

He received the EE and Ph.D. degrees in Applied Sciences from the Katholieke Universiteit Leuven, Belgium, in 1978 and 1983 respectively. From 1983-1985, he was a Visiting Research Engineer at UC Berkeley. From 1985-1987, he was a research manager at IMEC, Belgium, and in 1987, joined the faculty of the Electrical Engineering and Computer Science department at UC Berkeley, where he is now holds the Donald O. Pederson Distinguished Professorship. He has been a visiting professor at the University of Pavia (Italy), Waseda University (Japan), the Technical University Delft (Netherlands), Victoria Technical University and the University of New South Wales (Australia). He is currently the Scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the director of the Multiscale Systems Research Center (MuSyC).

Homepage: http://www.eecs.berkeley.edu/Faculty/Homepages/rabaey.html
Email:  Jan@eecs


Topics covered:

  • Design metrics: delay, power, cost robustness.
  • Operation and modeling of CMOS Devices
  • Device current-voltage characteristics for manual and SPICE analysis
  • Circuit simulation, SPICE
  • Static CMOS inverter: voltage-transfer characteristics
  • Advanced device parameters, process variations and scaling
  • Layout design rules
  • Layout editing, Cadence Virtuoso
  • Schematic entry, Cadence Analog Artist
  • CMOS Inverter: Dynamic behavior, equivalent resistances, propagation delay
  • MOS transistor capacitances
  • IC interconnect
  • Interconnect capacitance and resistance
  • Circuit extraction, checking
  • Standard complementary CMOS combinatorial logic gates
  • Propagation delay, capacitance, voltage dependence
  • Optimization for speed, method of logical effort
  • Standard and datapath cells, Euler diagrams
  • Ratioed logic, pseudo-NMOS logic
  • Pass-transistor logic
  • Dynamic and domino logic styles
  • Sequential logic: Flip-flops, latches, registers, multivibrators
  • Clocking and timing
  • Clock distribution, timing analysis
  • Driving interconnect, buffer design
  • Digital building blocks: Adders, multipliers, shifters
  • Memory design
  • SRAM DRAM Flash

64x32 SRAM block design. A large (14,000 transistor) circuit block is designed for minimum area and delay while meeting a set of defined constraints (noise margins and capacitances).


Spring 2014 - Rabaey