Lunch: 12:45 1:45pm
Open House: 2:00 - 4:00pm

Announcing a new 5-year research project that recognizes the shift from transistor-scaling-driven performance improvements to a new post-scaling world where whole-stack co-design is the key to improved efficiency. Building on the success of the soon to be completed Par Lab project, it uses deep hardware and software co-tuning to achieve the highest possible performance and energy efficiency for future mobile and rack computing systems.