The speed gap between the memory and processor core grows at an exponential rate due to the difference between their time constants for their exponential speedup. Therefore, memory is becoming increasingly more important in a system. The slower speedup rate for memory is fundamentally limited due to the communication required over the entire memory space. So, architectural advancement in memory is essential for filling this gap and for continuing the computer speedup. The first step in achieving this is to construct a formal model that can describe the existing memory architectures and to build an environment based on this model that can allow the architect to easily explore the interesting portion of the tradeoff spaces. Once the formal memory model and environment are developed, the memory design space can then be formally and hopefully automatically explored by leveraging the semantics behind the model. Determining the formal memory model and constructing a memory design exploration framework is the focus of my research.
In order to formalize the memory architecture, we must address the following issues. (1) How to model the memory structure uniformly across the levels of hierarchy. This includes the organization detail of the memory. (2) How to model the interactions across the memory hierarchy. This includes how read and write is done across the hierarchy and how pre-fetch behaves as a function of access history. (3) How to model the consistency issues across the hierarchy and multiprocessor memories. Currently within our memory model, these issues are models with tables and accessors that communicate by function call semantics. The consistency methods are modeled by arbitrators that orders concurrent incoming function calls. A framework is built on top of the model by providing a library of simple parameterized memory elements. This allows the designer to easily build a complex memory system by stacking together and configuring the simple elements. Simulation is available through the Ptolemy II kernel. A much faster simulation engine is in development by connecting to the Mescal simulator in the PE domain.
A formal memory exploration framework requires the following: a formal model of the specification, a formal description of the design space, a formal description of the cost functions, and a formal list of design space constraints. The formal memory model provides a partial language to describe these. Once these are fully determined, the exploration can be formulized as an optimization problem, where the goal is to find the best design according the cost function that in the valid design space and satisfies the specification. Since the design process is resource constrained, for example, time, heuristics may be required to maximize the chance to find the optimal design. Some examples of these heuristics are genetics algorithm and gradient descend. We will study when and which heuristics are required and how effective they are.
The final goal in the research is to use the above system to explore interesting memory architecture design space. It is hoped with the formality and automated method, a better memory design can be found in faster time.