A thin body (<10 nm) is essential for sub 50 nm MOSFETs. Our work with the planarized solid-phase epitaxy process succeeded in 2000. This year we will use a dummy layer on the SPE film to improve the crystalline quality of the channel. After selectively removing the dummy layer, we can get excellent channel film while keeping its ultra-thin thickness. Better device performance is expected from this new fabrication technique.
Besides the process difficulties associated with the ultra-thin body, the control of the threshold voltage becomes a big issue for ultra-thin body devices, because the body doping is not effective in tuning the threshold voltage. Gate work function is believed to be the only method for the right Vt. Various metal gates and silicide gates are going to be tested for the right work function and CMOS process compatibility. Silicide gate with various types of doping shows a continuous range of work function, which makes the material perfect as a gate. With the primitive result we have, silicide gate covers the work function range required by UTB and FinFET devices. Fabrication is in progress.
An analytical model for fully depleted thin SOI and double gate MOSFET is also in progress. We solve the Poisson equation in the thin body and can calculate the 2D potential profile. We investigate the effect of the high k dielectric and pocket doping. We can use the analytical results as a guide for device designing, incluing the device dimensions and doping profile.