Gate line edge roughness (LER) is the random deviation of gate line edges from an ideal definition. It can be produced in lithography and etching steps. LER does not scale down with line width and only reduces with improved process conditions. Recently, as the industry is pushing their logic development toward sub-50 nm physical gate lengths, gate LER is an increasing concern, for it potentially affects circuit performance and reliability. The LER effects on MOSFET device performance have been studied by us and several other research groups through device simulation. In cooperation with AMD, we also performed an experimental study of the effects of gate line edge roughness on the electrical characteristics of bulk MOSFET devices. The physical gate length of the devices ranged from 0.76 µm to 30 nm. Pronounced difference of the gate line edge roughness was introduced using special lithographical techniques. Poly gate LER was characterized with SEM in an approach we developed. In electrical characterization, we compared device data with different gate line edge roughness. We studied the yield, threshold voltages, and DIBL as well as the current universal curves of both NMOS and PMOS devices. The detailed results will be reported in our publication.
As the gate length of MOSFET devices shrinks down below 20 nm, double-gate device structures are emerging as a strong candidate, even considering the added process complexity. This is because double-gate structures have better control of the short channel effect and near ideal turn-off slope. A much lower leakage level can be maintained even with very small gate length. The FINFET device, which is a vertical double-gate MOSFET, has demonstrated such potential capability experimentally. Using device simulations, we have investigated the effects of process variations on the electrical behaviors of 20 nm symmetric double-gate MOSFET devices designed for low power application. First, we studied the effect of doping profile fluctuation. Double-gate devices with poly silicon gates must have very high channel doping in order to reach the desired threshold voltage. In this case, we find the 3s value of VT variation caused by random impurity placement could be very large. This confirmed the effort of our group to engineer the work function of gate materials and maintain low or intrinsic channel doping in FINFET devices. Second, based on the device design with intrinsic channel and ideal gate work function, we analyzed the change of device electrical parameters caused by the variations on physical parameters such as gate length, body thickness, and gate dielectric thickness. We found that quantum effect has great impact on the performance of devices at this scale. The device electrical behavior is most sensitive to small variations in body thickness while the variations of effective channel length and other physical parameters are less critical. Based on these results, we gave predictive estimation on the tolerance of the device to different process variations in circuit application.
I am also targeting to study the effect of process variation on circuit performance and carrier transport in the channel of FINFET devices. I will devote my research to developing techniques and collecting experimental data in this study.