Jie-Hong Jiang, Yunjian Jiang, Yinghua Li, Donald Chai, Alan Mishchenko1, and Tiziano Villa2
(Professor Robert K. Brayton)
(SRC) 683-004

MVSIS is an experimental software infrastructure for optimization and synthesis of sequential multi-valued logic networks. It is a network of nodes, where each node represents multi-valued relation. It is a structural representation of a non-deterministic finite automaton. The model is general enough for reasoning about formal verification, control synthesis, and synthesis for both hardware and software. It represents new synthesis challenges that were never addressed before. Some initial study is highlighted in [1].

Some synthesis results have been obtained for algebraic and Boolean optimizations, as presented in [2], which are extensions of corresponding algorithms in the binary domain. We intend to continue research in the technology independent optimization of such non-deterministic logic networks.

Technology dependent optimization techniques are also being studied for various applications. Binary encoding techniques have been studied for synchronous hardware implementations. We also research design flow and mapping techniques that produce delay-insensitive asynchronous circuits, which are more power efficient than their synchronous counterpart, and are correct by construction. For software synthesis in a hw/sw codesign context, we are studying efficient algorithms to generate fast code from an optimal generalized cofactoring structure.

A. Mishchenk and R. K. Brayton, "A Theory of Non-Deterministic Networks," Int. Symp. Boolean Problems, Freiberg Germany, 2002.
M. Gao, J-H. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, T. Villa, and R. Brayton, "Optimization of Multi-Valued Multi-level Networks," Int. Symp. Multiple-Valued Logic, Boston, MA, May 2002.
Y. Jiang and R. K. Brayton, "Software Synthesis from Synchronous Specifications Using Logic Simulation Techniques," Design Automation Conf., New Orleans, LA, June 2002.
1Postdoctoral Researcher, Portland State University
2Visiting Researcher, PARADES EEIG, Rome, Italy

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