The main barrier to full exploitation of SOI/CMOS performance and power is that the design and fabrication of a dedicated chip is a risky process because present tools are neither accurate enough nor efficient enough for fast turnaround and high probability of first-pass success. In this project we address the model accuracy issue. A critical element of all integrated system designs is the SPICE model. SPICE modeling is the standard approach for precise design of critical-path subcircuits in all large systems, as well as the basis for computing the look-up tables used for higher-level timing simulation. Recent versions of the BSIM3 model, based on the physics of short channel MOSFETs, very accurately represent the behavior of the current generation of bulk silicon devices at frequencies up to around 1 GHz. However, current models are inadequate for frequencies much above that, because the intrinsic input resistance and substrate resistance are ignored. Furthermore, the best widely available SOI model, BSIMSOI, does not represent floating body behavior accurately enough to simulate correct output characteristics of fully depleted (FD)SOI devices even at DC, and little is known of the SOI body charging effect at >1 GHz. We will develop an improved FDSOI model based on the existing BSIMSOI model. FDSOI transistors will be fabricated at MIT's Lincoln Laboratory with gate lengths of 180 nm and up, and they will be characterized by both DC and S-parameter measurements at frequencies up to 50 GHz. A new model which includes intrinsic input resistance and SOI floating body effects will be developed at UC Berkeley. The effort will focus initially on DC behavior and then move to representation of RF effects at a frequency of at least 10 GHz.
1Staff, MIT Lincoln Lab
2Visiting Professor, Hong Kong University of Science and Technology