Sub-10 nm FETs: Thin Body Back Gated Schottky Transistors

Varadarajan Vidya
(Professor Tsu-Jae King)
UC-MICRO Program

The rapid growth of the semiconductor industry has been enabled by transistor scaling to improve the performance and cost of integrated circuit products. Continued scaling of the MOSFET presents new technological challenges as fundamental material and process limits are approached. It would therefore be useful to investigate novel FET structures that could be simpler to fabricate and more scalable than the MOSFET.

In this project we are focusing on the fabrication and characterization of short-channel (Lg < 20 nm) thin-body Schottky-gate transistors. The chief advantage of this structure compared to the conventional MOSFET lies in its extreme simplicity of structure and fabrication. The transistor has no p-n junctions between the S/D and channel, thus eliminating the requirement of hyper-abrupt junctions. The structure is constituted of a metal semiconductor contact as the front gate and a MOS back gate to adjust the threshold voltage. The conduction through the device is essentially resistive (similar to a JFET) with the resistance of the channel being adjusted using the front and back gate voltages. The channel lies in the middle of a thin silicon layer, thus making the interface quality unimportant for performance. In order to have channel pinch off at low gate voltages and good drive currents at high gate voltages of about 0.6 V (as desired for sub 10 nm devices), it is essential to have a heavily doped thin silicon channel, with the silicon thickness not very critical. Also, unlike the double gate MOSFET, the alignment between the front and back gates is not important for good transistor performance.

A metal-semiconductor contact typically suffers from (1) a large leakage current and, (2) Fermi level pinning. In order to overcome the two issues, an extremely thin layer (5-10 A) of silicon nitride is proposed to be used as a front gate dielectric. With conduction through the middle of the channel, the interface quality is not going to be very critical to the transistor performance. Simulations of this structure were done using the device simulator MEDICI and the results were compared to comparable double-gate MOSFET structures. The drive currents and short channel effects are comparable to the MOSFET, with the MESFET showing a better short channel performance. The drive current and transconductance are slightly poorer, but other benefits of the device are compelling enough to pursue the device further.

The fabrication of this structure has been started with the first run being tried on a poly-silicon channel to evaluate the feasibility of this idea. Later on, emphasis shall be given on thin silicon film crystallization to improve the transistor drive current. In the future we propose to demonstrate that this device can be scaled down far beyond the MOSFET limits and, theoretically, all the way to atomic dimensions. With a simple process flow and a poly-silicon channel, it is likely to be a good candidate for 3D intregration of devices as well.


Send mail to the author : (vidya@eecs.berkeley.edu)


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