Processor design today is very much an art form. The architect comes up with a design to support an instruction set, creates a high level simulator, and then passes it on to the design team to implement. This process makes it hard for the architect to explore the design space, and requires the design team to rewrite much of the architect’s model. In this research we present a communication-aware methodology for turning a description of an instruction set architecture (ISA) into a potentially complicated microarchitectural implementation. The three major goals of this work are: reusability, correct by construction designs, and the automatic generation of control and binding logic.
Previous work has produced simple in-order pipelines along with their associated control logic. Through the methodology, we aim to achieve more complicated features such as out-of order execution, speculation, and caching. Instead of aiming for automatic synthesis, we break the process into a series of steps, allowing the design decisions to be considered one at a time, and be viewed separately from the functionality of the system. Each step transforms from the previous step through refinement, mapping, or relaxation