Programmable Peripherals

Christian Sauer1, Chidamber Kulkarni2, and Matthias Gries3
(Professor Kurt Keutzer)

Building blocks for application-specific programmable system-on-chip architectures can be classified into (multi-) processors, memory hierarchies, interconnection networks and peripherals. While in the design process a lot of emphasis is put on the first three, peripherals, including communication interfaces as the largest subset, are often underestimated and neglected.

Our analysis [1] for multimedia and network domains clearly shows that (1) peripherals and communication interfaces are a significant share of the system (btween 30 and 40 percent of die area), (2) there is a large number of heterogeneous peripheral functions even on a single chip, and (3) a single function can be even more complex than a processor core.

The main goal of this research is to achieve a reduction in the diversity of peripherals, thereby making the design process more regular and potentially simpler. We propose to achieve the goal by means of a programmable peripheral processor that can be targeted at multiple peripheral functions. The advantages of such a system are not only the unified design process, but also an increase in robustness of the overall system due to a regular software interface for device drivers.

[1]
C. Sauer, "Modeling Peripherals," Fully Programmable Systems Theme, GSRC Workshop, Stanford, CA, March 2002.
1Visiting Industrial Fellow, Infineon Technologies
2Postdoctoral Researcher
3Postdoctoral Researcher

Send mail to the author : (sauer@eecs.berkeley.edu)


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