Wireplanning in Logic Synthesis

Satrajit Chatterjee
(Professor Robert K. Brayton)
Semiconductor Research Corporation

In this work we are studying techniques for logic synthesis which lead to circuits which are "better" for placement and for routing. In the current framework, we still separate logic synthesis from physical design. We are trying to characterize properties of Boolean networks which allow for better layout. Thus in addition to the traditional literal count, we seek other metrics for boolean networks which may be better indicators of the wiring complexity during physical design. We hope to modify the traditional logic synthesis algorithms (which optimize for literal count) to optimize for a different cost function which takes into account these new metrics in addition to literal count.

Send mail to the author : (satrajit@eecs.berkeley.edu)

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