Josephson-CMOS Hybrid Memories Operating at 4 K

Qingguo Liu
(Professor Theodore Van Duzer)

Josephson-CMOS hybrid random-access memories have the potential to remove the memory bottleneck faced by Josephson digital technology. The main idea is to use high-density, charge-storage CMOS gates as the memory and access them by high-speed superconductive devices. This takes advantage of the best features of each. CMOS devices using the 0.25 micron process were fabricated and tested at 4 K, and a 4 K MOS device model was established, based on low-temperature experimental data on discrete devices. We intend to include the capacitances at low temperature based on measurements. According to the 4 K model, operating sub-micron CMOS devices at 4 K will further increase memory circuit speed as well as allow operation at low voltage, resulting in reduced power dissipation. In realizing such a memory hybrid, an interface circuit is needed to amplify millivolt-level Josephson data signals to volt-level signals for CMOS circuits. The interface circuit includes a higher-voltage Josephson pre-amplifier using a dual series array and an ultra-fast hybrid Josephson-CMOS amplifier, which incorporates an N-type MOSFET loaded with a series array of 400 Josephson junctions. The whole circuit has been simulated with a 4 K CMOS model, and a delay time less than 60 ps has been calculated in the absence of parasitic inductances and capacitances. That delay may be as much as doubled when accounting for parasitics. We designed and fabricated the interface circuit using a 0.25-micron National Semiconductor Corporation (NSC) process for the CMOS chip and the UC Berkeley 6.5 kA/cm2 Nb process for the Josephson chip. The circuit functionality has been experimentally verified by wire-bonding the CMOS chip to the Josephson chip. We demonstrated the design and fabrication of a model 64-kbit Josephson-CMOS hybrid memory, which includes the ultra-high-speed interface, address buffers, word line decoders, 3T DRAM-type cells, and Josephson sensing circuits; these are fabricated using the 0.25 micron NSC CMOS process and the UC Berkeley Nb process. Subnanosecond access time is predicted by a conservative simulation that used a room-temperature model for the CMOS. We are working on a piggyback structure using very short wire bonding with which we will be able to measure subnanosecond access times.

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