A Standard Model for SOI Circuit Design

Pin Su, Hui Wan, and Mansun Chan1
(Professors Chenming Hu and Ali Niknejad)
(SRC) 2000-NJ-795

Scaling and high performance advantages make SOI an important CMOS technology. However, the main barrier to full exploitation of SOI performance and power is that the design of an SOI chip is a relatively risky process because the relative lack of design experience makes it difficult to achieve fast turnaround and high probability of first-pass success. To surmount this barrier, a robust and physically accurate SPICE (compact) model is needed. SPICE modeling is the standard approach for precise design of critical-path sub-circuits in all large systems, as well as the basis for computing the look-up tables used in higher-level timing simulators. Cell libraries and IP blocks are in turn designed using the speedier simulations. A compact SOI MOSFET model is crucial to SOI circuit design. The goal of this work, therefore, is to establish a standard SOI model for the semiconductor industry.

1Visiting Professor, Hong Kong University of Science and Technology

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