The current trend in microprocessor design is characterized on the one hand by decreasing supply voltages (~1 V), regulation windows (~100 mV), and conversion ratios (1/12), and on the other hand by increasing supply currents (~100 A) and supply current slew rates (~50 A/us). These trends present a challenge to the design of microprocessor voltage regulation modules (VRMs). We are developing a VRM topology and a control strategy that can meet these requirements, while maintaining efficiency . Our design is based on a multi-phase buck converter supplemented by a low-inductance output clamp to handle fast output unloading transients (Figure 1).
We have analyzed the response of the buck converter under fast output current transients, and we have developed sensing and control methods for its implementation with a digital PWM controller [2,3]. This analysis has been done in the framework of low effective series resistance (ESR) ceramic capacitors, which are the expected choice for the next generation VRMs. We have further explored the effect of power train parameter variations on the current matching among the phases of the converter, and are currently working on an online multi-phase current sharing optimization scheme.
We are currently building a second generation digitally controlled VRM prototype with an FPGA-implemented controller to test the topology in Figure 1, as well as various control and optimization concepts.
Figure 1: Four-phase VRM with low-inductance clamp to ground