This research supports the PicoRadio project at the Berkeley Wireless Research Center. This project is focused on developing an extremely low-power, wireless sensor node capable of collecting data from the environment and transmitting it over an ad-hoc multihop network.
Phase III of this project involves system level architecture options to meet the aggressive 100 µW average power consumption requirement. Work to this end falls into two categories: power budgeting and architectural choices. A preliminary power budget for the PicoNode III has been created through analysis of the expected data rates, clock frequencies, projected 0.12 µ process characteristics, and discussions with the PicoNode subgroups. As more refined microarchitectures are explored for the various subcomponents, this power budget will be revised to provide a more accurate account of the power consumption.
The second category involves architectural options for low-power operation of the PicoNode. Known techniques for low-power design include clock gating, dynamic frequency scaling, multiple supply voltages, and dynamic threshold voltage scaling. Coupled with the event driven nature of sensor and communication networks, blocks can be powered down completely while waiting for events. Clearly the power management can no longer be an afterthought of the design, since it affects the partitioning of the system, design of the individual components, and interactions between them. One current vision uses a distributed power management scheme that would activate blocks upon the receipt of an event. However, while this strategy may minimize the active power of a particular block, it may not yield the globally minimal power consumption for the entire system due to the overhead of entering and exiting the power-down modes. In situations where data moves predictably through the system, a centralized controller can be used to optimize the power characteristics of these specific scenarios. Another current research topic involves maintaining the state of the system while using aggressive power reduction schemes in sleep mode.