Algorithms and VLSI Implementations of Low Power Digital Baseband Timing Recovery Systems for Wireless Communications

M. Josie Ammer
(Professor Jan M. Rabaey)
BWRC member companies, (DARPA) PAC-C program, and National Science Foundation

This research addresses the algorithms and implementations for digital baseband timing recovery in wireless receivers. Timing recovery refers to the estimation and tracking of several non-idealities in the received signal caused by (1) the wireless channel itself, and (2) the RF and analog circuits in the transmitter and receiver. Parameters to be estimated include: (1) frequency, (2) phase, (3) sampling instant, and (4) gain, including multipath and scattering effects. This research looks specifically at timing recovery performed on the baseband signal (after down-conversion from the carrier) in the digital domain (after the analog to digital converter) and is particularly concerned with lowering the power consumption of the total receiver.

Digital baseband timing recovery can ease the design of the analog and RF circuitry by correcting for non-idealities caused by sub-optimal implementations. This tradeoff becomes especially important in single-chip radios when the RF and analog circuitry needs to be implemented in an ostensibly digital process with low voltages--a difficult task. By transferring some of the complexity to the digital domain, it is conjectured that the entire system can consume less power. This work is taking place within the PicoRadio project where low power is the primary goal. We investigate the architectural and implementation issues related to building low power baseband timing recovery systems in VLSI.

In this research, the computational hardware requirements for timing recovery on the various PicoRadio physical layers provide a platform for evaluation of the digital baseband timing recovery systems. The past accomplishments and ongoing efforts include modification of algorithms, and the efficient mapping of these algorithms into architectures and VLSI implementations that provide the final measure of complexity and power consumption.

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