Mapping Concurrent Applications onto Architectural Platforms

Andrew Mihal
(Professor Kurt Keutzer)
Gigascale Silicon Research Center

The embedded system design process is characterized by three challenges. One challenge is the task of modeling heterogeneous concurrent applications. Another is the task of finding a programming model for heterogeneous multiprocessor architectural platforms. Compounding each of these challenges is the task of implementing heterogeneous applications on heterogeneous architectures. We believe that the key problem underlying each of these challenges is the modeling of concurrency, and the key to modeling concurrency is to capture concurrent communication formally in models of computation [1].

The aim of this research is to develop a disciplined approach to the design and implementation of communication structures in embedded applications. Our approach combines the network-on-chip paradigm with the models of computation paradigm. We use models of computation to capture the communication requirements of an application as well as to abstract the capabilities of a communication architecture. Then, application requirements and architectural capabilities are matched using a discipline based on network-on-chip principles.

Our design methodology is based on the Y-chart [2]. The Y-chart is an iterative strategy for design space exploration that enables the co-evolution of hardware and software. We extend the multiple views methodology [3] to provide designers with the right abstractions for implementing heterogeneous, concurrent applications on heterogeneous multiprocessor programmable platforms.

E. A. Lee, "Computing for Embedded Systems," IEEE Instrumentation and Measurement Technology Conf., May 2001.
B. Kienhuis, E. Deprettere et al., "A Methodology to Design Programmable Embedded Systems," SAMOS: Systems, Architectures, Modeling, and Simulation, ed. F. Deprettere et al., LNCS series, Springer-Verlag, Vol. 2268, November 2001.
A. Mihal, C. Kulkarni et al., "A Disciplined Approach to the Development of Architectural Platforms," IEEE Design and Test of Computers, November/December 2002.

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