Industrial FinFET Fabrication Using Standard Processing Tools

Leland Chang
(Professors Jeffrey Bokor, Chenming Hu, and Tsu-Jae King)
(SRC) 850.002

Transistor scaling below 50 nm gate lengths will likely require the incorporation of new device structures in order to adequately control short-channel effects. A promising candidate is the FinFET, a double-gate MOSFET structure [1,2]. The device consists of self-aligned double gates surrounding a thin silicon slab (the “fin”), which can sufficiently suppress short-channel effects.

Thus far, device fabrication has taken place in a research environment and can consequently make use of non-standard tools such as electron beam lithography. In this work, a manufacturable FinFET process is developed using standard processing tools found in an industrial fabrication facility. Critical process steps have been evaluated using short-loop experiments, and initial device results have been obtained. Working transistors down to 10 nm in gate length have been successfully fabricated. Continued work will focus on achieving appropriate threshold voltages in order to study circuit performance.

[1]
X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub 50-nm FinFET: PMOS,” Int. Electron Devices Mtg., Washington, DC, December 1999.
[2]
Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET Process Technology for Nanoscale CMOS,” Int. Electron Devices Mtg., Washington, DC, December 2001.

Send mail to the author : (leland@eecs.berkeley.edu)


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