The Theory of Latency Insensitive Design

Luca Carloni and Kenneth L. McMillan1
(Professor Alberto L. Sangiovanni-Vincentelli)
Semiconductor Research Corporation

The theory of latency insensitive design is the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components [1]. Latency insensitive designs are synchronous distributed systems and are realized by composing functional modules that exchange data on communication channels according to an appropriate protocol [2]. The protocol works on the assumption that the modules are stallable, a weak condition to ask them to obey. The goal of the protocol is to guarantee that latency insensitive designs composed of functionally correct modules behave correctly independent of the channel latencies. This allows us to increase the robustness of a design implementation, because any delay variations of a channel can be "recovered" by changing the channel latency while the overall system functionality remains unaffected. As a consequence, an important application of the proposed theory is represented by the latency insensitive methodology to design large digital integrated circuits by using deep sub-micron technologies [3].

[1]
L. P. Carloni, K. L. McMillan, and A. L. Sangiovanni-Vincentelli, "Theory of Latency-Insensitive Design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 9, September 2001.
[2]
L. P. Carloni, K. L. McMillan, and A. L. Sangiovanni-Vincentelli, "Latency Insensitive Protocols," Proc. Int. Conf. Computer-Aided Verification, Trento, Italy, July 1999.
[3]
L. P. Carloni, K. L. McMillan, A. Saldanha, and A. L. Sangiovanni-Vincentelli, "A Methodology for Correct-by-Construction Latency-Insensitive Design," Proc. ICCAD, San Jose, CA, November 1999.
1Cadence Berkeley Laboratories

More information (http://www-cad.eecs.berkeley.edu/~lcarloni/) or

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