Selective SiGe CVD Process for Raised-S/D FinFET Application

Kyoungsub Shin
(Professor Tsu-Jae King)

Selective deposition of SiGe is advantageous for making a raised S/D FinFET with very low parasitic resistance, particularly needed for analog circuit applications. Ideally, the Ge content should be limited to less than 50% to simplify the S/D silicidation process. In this project, we will explore the use of Cl2 gas to enhance the selective deposition of low-Ge-content films on Si (vs. SiO2 or Si3N4) in a conventional LPCVD furnace. The chlorine is expected to promote selective deposition by removing ad-atoms on the insulator surface via SiCl2 or GeCl2 desorption, at temperatures above 700°or 400°, respectively. The gas flow ratios and process temperature will be optimized for high selectivity of deposition.

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