As the double-gate MOSFET (DG-MOSFET) structure is adopted for CMOS IC manufacturing in the sub-30 nm gate-length regime, the effects of process-induced variations on DG-MOSFET characteristics become very critical. In this research, we compare n-channel symmetric-double-gate (SDG) and asymmetric-double-gate (ADG) devices with nominal gate length of 9 nm in terms of their tolerance to process induced variations. The SDG device is assumed to have a gate material with work function 4.486 eV, while the ADG device is assumed to have n+/p+ poly-Si front-gate/back-gate. MEDICI device simulation is used, with a drift diffusion model for carrier transport and a realistic device structure based on ITRS specifications for the 9 nm technology generation. The results show that both ADG and SDG have acceptable performance within 25% bottom gate misalignment, 10% CD variation, and 5% Tsi variation. Thus, ADG and SDG are both fairly tolerant to process-induced variations. Quantum-confinement effects are more severe in the case of the ADG device and can be dominant for ultra-thin body thickness Tsi, however. Overall, the SDG structure seems to be more advantageous, which implies that metal gate technology will be needed to fully tap the circuit-performance benefits of the DG MOSFET structure.