Microprocessors, both general purpose and application-specific, are inherently limited by a small amount of instruction-level parallelism (due to branches, precise interrupts, etc.) and increase in performance primarily through scaling of the core clock frequency. Although partially mitigated by improved process technologies, each increase in performance comes with a corresponding increase in power consumption.
This research will investigate hardware-based general purpose computing without any use of the von Neumann software architecture. The Berkeley href="http://bwrc.eecs.berkeley.edu">BWRC, will be used to develop the methodologies for computing purely with hardware and investigate how to maximally benefit from parallelism in the absence of a sequential instruction stream. Emphasis will be placed on translating the well-understood semantics of sequential programming (such as function libraries, processes/threads, and address spaces) into their corresponding constructs in hardware, as well as evaluating flexible and scalable computing fabrics (such as ALU meshes and neural networks) which map well into the incremental configuration features of FPGAs.