Simple Parameter Extraction for Short Channel FET Current and Delay Models

Joshua Garrett
(Professor Borivoje Nikolic)

Simple, accurate short channel MOSFET current and delay models are useful in low-power digital design for rapidly evaluating the effect of changing transistor width, supply, and threshold voltage. As device channel lengths have scaled, effects such as mobility degradation and velocity saturation have made the Shockley square-law model insufficient for accurate characterization. Two accurate short channel current models have been presented in [1] and [2]. In this research it is shown the second model can be simplified such that only three extracted parameters are necessary to model the velocity saturation and mobility degradation behavior, covering both triode and saturation operating regions, and these parameters can be easily extracted from transistor I-V curves. This simplified model is demonstrated both on a commercial 0.13 µm process technology and a simulated 20 nm FinFET technology. Furthermore, it is demonstrated that the form of both models can be used in delay expressions that accurately capture inverter delays across a range of supply voltages and fan-outs.

[1]
T. Sakurai and A. Newton, “Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and other Formulas,” IEEE J. Solid-State Circuits, Vol. 25, No. 2, April 1990.
[2]
C. Sodini, P. Ko, and J. Moll, “The Effect of High Fields on MOS Device and Circuit Performance,” IEEE Trans. Electron Devices, Vol. 31, No. 10, October 1984.

Send mail to the author : (joshuag@eecs.berkeley.edu)


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