Next Generation Highly Integrated Wireless Sensor Network Platform

Jason Hill
(Professor David E. Culler)
(DARPA - NEST) F33615-01-C-1895

Emerging low-power, embedded wireless sensor devices are targeting a wide range of applications, yet have very limited processing, storage, and energy resources. An architecture must be developed that can efficiently meet system demands while simultaneously remaining flexible to application specific optimizations. To answer the demands of application specific operations, we are building an integrated CMOS version of the Berkeley motes wireless sensor platform. A prototype chip that included CPU, ADC, communication accelerators, and memory was designed and fabricated by National Semiconductor as shown in Figures 1 and 2. Measuring just 2 mm x 2 mm, it represents a significant reduction is size, cost, and power over current generation motes. The test chip was not fully functional, but it could successfully execute instructions and demonstrate basic I/O capabilities. A second generation of this node has been designed and is currently being fabricated. In addition to fixing the minor bugs in the first prototype, this second generation chip includes support for multiple register sets, data encryption, and it is equipped with a CMOS RF transmitter. The transmitter architecture uses a 32 Khz crystal as a reference oscillator and frequency lock for a capacitor array based VCO to a 900 Mhz transmission frequency.

Figure 1: TinyOS network stack accelerator

Figure 2: Floorplan for the mote chip

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