An Integrated, Low Power, Ultra-Wideband Transceiver for Low-Rate, Indoor Wireless Systems

Ian D. O'Donnell, Mike S. W. Chen, and Stanley B. T. Wang
(Professor Robert W. Brodersen)
(MURI) 065861 and (ONR) N00014-00-1-0223

In current attempts at low-power, single-chip, integrated radio solutions, the analog circuitry tends to consume a majority of the total power. Tight RF requirements on the front-end receivers, and large transmit powers necessary for long distances and high signal-to-noise ratios, constrain a design with difficult, if not impossible, specifications to implement in very low power in low-cost CMOS technology. While low-power digital techniques for large-scale designs exist and are being actively applied, no comparable techniques have emerged yet for the analog design components. Current trends suggest that the while the speed and energy efficiency of digital circuits will improve with the lower supplies and smaller geometries, analog circuits are actually hampered by the supply reduction. This suggests a sort of "Holy Grail" for radio design, which eliminates as much as possible the necessity for analog components. This radio would ideally convert the incoming antenna signal to a binary value and then perform all processing digitally, yielding an implementation with all of the benefits digital design has to offer (full integration, lower power, cheaper technology, robustness, the ability to implement complex algorithms such as adaptation, maximum likelihood estimation, etc.) While current radio standards would require a very fast and high accuracy A/D, we believe that by using a pulse-based, ultra-wideband (UWB) signaling scheme we can approach this fully-digital, fully-integrated radio; reducing both transmit power and the receiver's analog complexity beyond simply scaling a traditional narrowband transceiver.

The focus of this research is the design of such a "fully-digital" single-chip radio transceiver. We assume no special or fixed building infrastructure; the radios will be able to communicate flexibly in both peer-to-peer or broadcast modes. The target cell-size is approximately 5-10 meters with an estimated maximum of 32 active users at one time per cell. The anticipated bit-rate will be around 100 kb/s (uncoded BER ~1e-3) with a total 1 mW (TX+RX) power budget for the transceiver. A narrow pulse (approximately 1 ns wide) is transmitted using simple digital switches; spreading energy over a Gigahertz of bandwidth. Reception, after wideband gain and filtering, occurs in a bank of A/D converters which capture the received pulse in an adjustable window of 16 to 64 ns (shown in Figure 1). This window is composed of 32 to 128 data samples at a 2 GHz rate and is repeated at the pulse broadcast frequency which may range from 62.5 MHz to roughly 1 MHz. The digital backend (shown in Figure 2) aggregates these windows into a block of 256 samples which is fed into a bank of 128 parallel matched filters of length 128 samples each with 5-bit programmable taps. The outputs of these matched filters are sent to either an acquisition or synchronization block. The synchronization block implements early-late correlation for tracking, and the acquisition block contains 11 de-spreading correlators in parallel as a compromise between area and search time. Once a correlation peak above the programmable threshold is found by the peak detector logic, the backend switches from acquisition to tracking mode. For flexibility, separate spreading codes may be used for acquisition and synchronization and both may be of length 1 to 1024 chips.

In addition to communication, the ability to do some form of ranging or localization is a considered a necessity. Due to the fine time resolution inherent to UWB, accuracy on the order of several feet is possible and research into robust ranging algorithms has begun. Also, as extreme low cost and high integration are desired, we are investigating PCB/circuit co-design for the antenna and matching elements, and targeting a generic, digital CMOS IC process for fabrication.

Figure 1: Analog frontend block diagram

Figure 2: Digital backend block diagram

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