Reliable VLSI Design in the Nanometer Regime

Huifang Qin and Ruth Wang
(Professor Jan M. Rabaey)

Scaling of CMOS technology poses significant difficulties in precise process control and circuit operation noise reduction. In order to continue the silicon success in the nanometer regime, it is critical to explore design solutions to handle the performance variability at the early stage. Our work aims at building a cohesive process and design co-optimization framework for future technology generations. By developing a set of predictive technology and circuit performance models, current efforts are focused on investigating the impact of variations on different digital circuit designs at both gate level and micro-architecture level.

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