Systematically Exploring the Design Space of Network Processors

Matthias Gries1, Chidamber Kulkarni2, and Christian Sauer3
(Professor Kurt Keutzer)
GSRC

Current designs of network processors reveal manifold micro-architectures [1]. Even processors targeted on the same application domain show a variety of differences in micro-architecture topology. It is unclear whether any of the current solutions actually represents a natural and efficient implementation of the required functionality for a given application such as IPv4 forwarding.

In order to enable the systematic evaluation of different existing innovative designs in a reasonable time-frame, we investigate the feasibility of a recently developed analytical performance estimation approach [2] to catch inherent characteristics of the design space and to automatically guide the designer toward optimal solutions in the network processing domain.

We focus in particular on the following issues: (1) extension of the analytical approach to the model and automatically exploring heterogeneous communication architectures; (2) comparison of results from the analytical model with simulation-based results [3]; (3) design space pruning by incorporating technology constraints as well as individual constraints defined by the designer; and (4) incorporation of domain-specific design decisions into an automated exploration framework, such as the partitioning of application tasks between micro-processor threads.

[1]
N. Shah, "Understanding Network Processors," master's thesis, UC Berkeley, September 2001.
[2]
L. Thiele, S. Chakraborty, M. Gries, A. Maxiaguine, and J. Greutert, "Embedded Software in Network Processors--Models and Algorithms," Workshop on Embedded Software, Tahoe City, CA, October 2001.
[3]
M. Tsai, C. Kulkarni, C. Sauer, N. Shah, and K. Keutzer, "A Benchmarking Methodology for Network Processors," Network Processors 2002: Design Principles and Practice, Morgan Kaufmann Publishers Inc., 2002.
1Postdoctoral Researcher
2Postdoctoral Researcher
3Visiting Industrial Fellow, Infineon Technologies

Send mail to the author : (gries@eecs.berkeley.edu)


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