HfO2 is one of the most promising candidates to replace SiO2 as the gate dielectric because of its high permittivity, thermodynamic stability, and large energy-bandgap offset to Si. For simplicity of process integration, polycrystalline silicon (poly-Si) is preferred as a gate electrode material. However, the growth of an interfacial layer at the surface of the silicon upon high-temperature annealing (e.g., used for source/drain formation) increases the equivalent oxide thickness (EOT) and gate leakage current .
Polycrystalline silicon-germanium (poly-SiGe) has received much attention as an alternative gate-electrode material, because it alleviates gate depletion and boron penetration issues . Recently, it was reported that the use of poly-SiGe results in thinner EOT for HfO2 gate dielectric .
We investigate the mechanism responsible for this effect. Using MOS capacitors, the effect of the gate material and gate deposition rate on interfacial layer formation is studied. A conventional LPCVD furnace was used to deposit the gate materials (poly-Si and poly-Si0.8Ge0.2) at 550°C onto PVD HfO2 gate dielectric. The effect of gate deposition rate was studied by comparing the results for poly-Si deposited using SiH4 against those for poly-Si deposited using Si2H6. (The deposition rate for poly-Si using Si2H6 is about 8 times faster than that for poly-Si using SiH4; the deposition rate for Si0.8Ge0.2 is about 7 times faster than that for poly-Si using SiH4).