Controllability of off-state leakage current, with retention of large on-state drive current, is the primary challenge for scaling complementary metal oxide semiconductor (CMOS) transistor gate lengths into the nanoscale regime. Fully depleted ultra-thin-body (UTB) SOI metal oxide semiconductor field effect transistor (MOSFET) structures provide excellent suppression of short channel effects and performance improvement, and hence are promising for sub-70 nm CMOS technology . In order to avoid mobility degradation and threshold-voltage (VT) variation due to channel dopant fluctuations, it is desirable to use an undoped or very lightly doped (<1017 cm-3) silicon body. In this case, VT adjustment must be achieved by gate work function engineering, in the range from 4.4-5.0 V for a fully depleted SOI CMOS technology . Ideally, the technique for adjusting the gate work function should not utilize common dopants in Si, in order to avoid problems due to dopant penetration through ultra-thin gate dielectrics during the source/drain (S/D) annealing step(s). These requirements essentially rule out polycrystalline silicon (poly-Si) as a candidate gate material for nanoscale UTB SOI CMOSFETs. For simplicity of process integration, it is preferable to deposit a single gate material and subsequently adjust its work function selectively (e.g., in the n-channel vs. p-channel regions) as required. Molybdenum (Mo) is applied as the gate material to achieve the proper VT (-0.2 V) in p-channel UTB SOI MOSFETs for the first time, and VT adjustment via nitrogen implantation is demonstrated. Continued work will focus on investigating the statistical variation of the threshold voltage due to the nitrogen implantation and achieving appropriate threshold voltages with high-K dielectric (HfO2).