The 4G Wireless LAN demands a high data rate, such as multi-gigabits/s. The need for such a high data rate Wireless LAN has prompted the Federal Communications Commission (FCC) to release 5 GHz of unlicensed spectrum, from 59 GHz to 64 GHz.
In 60 GHz radio systems, there is not only a high frequency operation issue but also a baseband processing issue. In the case that we operate five channels in a 5 GHz band, one channel of bandwidth is 1 GHz. In order to process a 1 GHz bandwidth channel, we need a 4 GS/s A/D converter, which doesn't bode well either in the realization of such an A/D converter or in the digital signal processing after A/D conversion.
One of the conventional approaches for meeting the high-speed requirement is a time-interleaved parallel A/D converter. At the sampling rate of 4 GS/s, it suffers from path mismatch, marring system performance, and adds the complexity of digital error calibration. Even after A/D conversion, the digital signal processing speed is still 4 GHz.
One of the promising communication modulation schemes for wideband applications is orthogonal frequency division multiplexing (OFDM). OFDM consists of multiple subcarriers, and each subcarrier is orthogonal to the other subcarriers. 60 GHz radio systems consider OFDM to be the strong candidate for the modulation schemes. The new idea came from the unique characteristics of OFDM.
The key idea of parallel path receiver architecture is that a wideband OFDM channel can be split up into a number of uncorrelated narrow band OFDM subchannels. For example, a 1 GHz channel has 200 MHz of guard band and 800 MHz of information channel with 1024 OFDM subcarriers. When we split up the 800 MHz bandwidth channel into 8 subchannels, each subchannel has 100 MHz bandwidth with 128 OFDM subcarriers. We just need to process 100 MHz of bandwidth with 400 MS/s A/D converter, but we need to have eight copies of the same blocks. This approach doesn't suffer from the path mismatch problem. 400 MS/s A/D converter is easy to design and the digital signal processing can be run with 400 MHz, which implies a low energy solution.
From the circuit design perspective, the important circuit building blocks are mixers and frequency synthesizers, because they are sensitive to cross talks. Parallel mixers are exposed to the possible cross modulation. Frequency synthesizers are vulnerable to the cross harmonics. This research project places emphasis on the demonstration of parallel mixers and frequency synthesizers operating against two cross talks. Another issue is the reasonable power consumption for the parallel mixers and multiple frequency synthesizers.
The test structure of mixers and frequency synthesizers will be designed with 0.13 µm CMOS. There are four parallel paths. The operating intermediate frequency is 2.5 GHz. The subchannel bandwidth is 50 MHz. The circuit topology of mixers is a parallel folded active mixer with current bleeding. This topology reduces the effective input loading and power consumption of parallel mixers and isolates the cross modulation. The circuit topology of frequency synthesizers is a mixer-based frequency synthesizer, which eliminates the frequency divider.