Compact Modeling of Double-Gate MOSFETs

Chung-Hsun Lin and Mansun Chan1
(Professor Chenming Hu)
(SRC) 2002-NJ-1001

As the microelectronics industry is fast approaching the limit of bulk CMOS scaling, there are extensive research activities on double-gate MOSFETs which can potentially further extend CMOS scaling to 10 nm gate dimensions. The topology of the double-gate device is fundamentally different from that of a bulk or SOI device in that the second gate can be either tied together with the first gate or biased separately. The implications of the additional feature on circuit performance need to be understood and evaluated at the circuit level with a sound compact model. As a result, there is a strong demand on a compact model that can be implemented into the existing circuit simulation infrastructure.

The goal of this project is to develop a generic non-structural dependent compact model for double-gate CMOS, implemented in the BSIM framework. The model will be physics-based and general enough to cover various structures of double-gate MOSFETs. The model will also account for arbitrary work functions and separately controlled gates. From a circuit application perspective, the compact model will be widely applicable to different biasing schemes, e.g., both gates switching or separately biased (DC or AC). The ultimate objective is to provide a predictive yet versatile tool for circuit designers to evaluate the performance benefits of the general and specific features of a double-gate MOSFET technology, thus giving a guideline to the selection of double-gate structures.

1Visiting Professor, Hong Kong University of Science & Technology

Send mail to the author : (chl@eecs.berkeley.edu)


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