High Performance A/D Interface Circuits for Wireless Applications

Yun Chiu
(Professor Paul R. Gray)
Intel PhD Fellowship

The great success of the digital CMOS IC technology during the last ten years has firmly built up the dominance of CMOS as the mainstream silicon technology of the IC industry. The everlasting pursuit for high integration and low cost has also endorsed the design methodology known as the "system-on-chip" approach. But integrating noise-sensitive, high-sensitivity analog and RF circuits on the same die with noisy digital signal processing (DSP) circuits switching at high frequencies is a very challenging task for circuit designers. The demand for wide bandwidth of the analog front-end exacerbates the problem since the designer cannot benefit from most of the narrow-band techniques, such as noise shaping and filtering. This underlines the need for innovation of broadband, power-efficient analog circuit techniques that also feature high dynamic range.

Among these challenges, the analog-to-digital interface circuit is one of the most difficult to deal with and can often consume 50% of the total receiver power. This underlines the research effort for innovations of analog circuit techniques in the deep-submicron regime. This research project will investigate these limitations and propose new techniques that ameliorate strong tradeoffs among power, accuracy, and bandwidth of the A/D interface circuits.


More information (http://kabuki.eecs.berkeley.edu/~chiuyun/) or

Send mail to the author : (chiuyun@eecs.berkeley.edu)


Edit this abstract