Semiconductor memories such as DRAM play an increasingly important part in determining the performance of microelectronic products. Their role has raised the demand for reliable, high density memories with fast data access and low power consumption. However, significant challenges must be overcome in scaling DRAM. Reducing the transistor's off-state leakage, for example, can require high substrate doping to sustain a large threshold voltage. Unfortunately, this approach enhances trap-assisted tunneling and leads to tail bits with small retention times. Another problem is the integration of a small storage capacitor in a technology which should provide an adequate sensing signal margin, long retention time, and soft error protection. As a result, it is unclear if DRAM can scale below feature sizes of 100 nm without changes in the standard 1 transistor/1 capacitor (1T/1C) cell design.
In this study, we investigate three new approaches at scaling DRAM. First, double-gate DRAM (DG-DRAM) is a new memory technology which embodies a thin body, double-gate structure. Scalability is intrinsic to its unique, compact design. We have compared DG-DRAM against other capacitorless DRAM technologies, considered variations in its cell design, performed experimental and simulation measurements, and explored soft error problems. In addition, two other capacitorless memory concepts are investigated. These include an improved version of a direct tunneling floating gate device, featuring a large threshold voltage window and superior data retention. A new direct tunneling, trap-based memory technology is also developed using conventional CMOS materials. These ideas represent novel and manufacturable approaches at bridging the gap between current CMOS memories and future technologies.