Double-gate (DG) MOSFETs are a proposed solution to extended CMOS scaling beyond bulk-Si MOSFETs. A variety of DG structures have been proposed . Vertical structures, such as the FinFET have a layout penalty related to the routing of wires to both the gates. A planar DG can be seen as a possible solution to such a problem. An experimental feasibility study for a self-aligned double gate structure has been proposed . In this present work, the work is being extended to produce sub 50 nm DG MOSFETs with Mo-gates to reduce gate depletion effects. Currently the feasibility of using such an approach for sub 50 nm DG structures is being investigated using a back-side illumination process on quartz substrates. After that, transistors will be fabricated using a similar approach. In parallel, simulation studies on device optimization are being pursued to optimize the circuit performance of DG MOSFETs.