Digital Calibration for Low-Power High-Performance A/D Conversion

Boris Murmann
(Professor Bernhard E. Boser)
Analog Devices and (UC Micro) 01-006

Digital signal processing in system-on-chip applications has created a need for high performance ADCs that are compatible with deep sub-micron technology. These applications typically demand high linearity, speed, and resolution while maintaining low power consumption. While digital circuits benefit from the aggressive downscaling of CMOS technology, the trend of decreasing supply voltage in deep sub-micron processes tends to increase the power dissipation of high resolution ADCs. This research focuses on a novel concept through which analog domain precision can be traded off for low power digital signal processing.

In most high-speed pipelined A/D converters, high-gain residue-amplifiers dominate overall power dissipation. Substantial power savings are possible when precision amplifiers are replaced by simple open-loop gain stages. To take advantage of this opportunity, we propose a new digital calibration technique capable of correcting errors arising from amplifier nonlinearity and temperature drift. Our approach uses a statistics-based signal processing technique to measure and cancel gain- and nonlinearity errors of the imprecise, low power residue amplifiers. Critical converter stages are switched randomly between two transfer characteristics without interrupting normal A/D operation. Comparison of the two distinct cumulative distributions in the converter back-end allows estimation of the required calibration parameters.

To evaluate the proposed scheme, we have designed and implemented a 12-bit, 75 Msample/s prototype ADC in 0.35 m CMOS technology [1]. For simplicity, the digital calibration is applied only to the first converter stage and implemented off chip. Compared to a state-of-the-art reference design [2], we achieve more than 60% power savings in this critical portion of the ADC. Measurement results show that the digital post-processing technique improves the signal to noise + distortion ratio (SNDR) of the converter from 48 dB to 67 dB. Future work will focus on expanding the concept to multi-stage calibration applied to a high performance design in a low-voltage, deep-submicron technology.

Figure 1: Chip micrograph

B. Murmann and B. E. Boser, A 12 b 75 Msample/s Pipelined ADC Using Open Loop Residue Amplification, IEEE Int. Solid State Circuits Conf., 2003 (to appear).
D. Kelly et al., A 3 V 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist, IEEE Int. Solid State Circuits Conf., San Francisco, CA, February 2001.

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