Abstracts for Theodore Van Duzer

The EECS Research Summary for 2003


Josephson-CMOS Hybrid Memories Operating at 4 K

Qingguo Liu
(Professor Theodore Van Duzer)

Josephson-CMOS hybrid random-access memories have the potential to remove the memory bottleneck faced by Josephson digital technology. The main idea is to use high-density, charge-storage CMOS gates as the memory and access them by high-speed superconductive devices. This takes advantage of the best features of each. CMOS devices using the 0.25 micron process were fabricated and tested at 4 K, and a 4 K MOS device model was established, based on low-temperature experimental data on discrete devices. We intend to include the capacitances at low temperature based on measurements. According to the 4 K model, operating sub-micron CMOS devices at 4 K will further increase memory circuit speed as well as allow operation at low voltage, resulting in reduced power dissipation. In realizing such a memory hybrid, an interface circuit is needed to amplify millivolt-level Josephson data signals to volt-level signals for CMOS circuits. The interface circuit includes a higher-voltage Josephson pre-amplifier using a dual series array and an ultra-fast hybrid Josephson-CMOS amplifier, which incorporates an N-type MOSFET loaded with a series array of 400 Josephson junctions. The whole circuit has been simulated with a 4 K CMOS model, and a delay time less than 60 ps has been calculated in the absence of parasitic inductances and capacitances. That delay may be as much as doubled when accounting for parasitics. We designed and fabricated the interface circuit using a 0.25-micron National Semiconductor Corporation (NSC) process for the CMOS chip and the UC Berkeley 6.5 kA/cm2 Nb process for the Josephson chip. The circuit functionality has been experimentally verified by wire-bonding the CMOS chip to the Josephson chip. We demonstrated the design and fabrication of a model 64-kbit Josephson-CMOS hybrid memory, which includes the ultra-high-speed interface, address buffers, word line decoders, 3T DRAM-type cells, and Josephson sensing circuits; these are fabricated using the 0.25 micron NSC CMOS process and the UC Berkeley Nb process. Subnanosecond access time is predicted by a conservative simulation that used a room-temperature model for the CMOS. We are working on a piggyback structure using very short wire bonding with which we will be able to measure subnanosecond access times.


Send mail to the author : (qgliu@eecs.berkeley.edu)

Internally Shunted Josephson Junctions for Ultra-High Speed Logic*

Xianghui Zeng1 and Xiaofan Meng2
(Professor Theodore Van Duzer)
(ONR) N00014-00-1-0003

Superconducting niobium integrated circuit technology employing Josphson tunnel junctions is well established, reliable, and reproducible. It has been used to make circuits with 70,000 junctions on a chip and has the potential for making single flux quantum (SFQ) circuits that operate at 50 GHz and above with extremely low power dissipation. However, it is not the ideal technology for these circuits, since the tunnel junctions must be shunted with resistors to yield the needed I-V characteristics. The goal of this project is to provide a replacement for the tunnel junction and its shunt resistor in the form of an internally shunted Josephson junction. The elimination of the external shunt not only saves space, but also avoids steps in the fabrication process and minimizes parasitic inductances that complicate circuit design and are detrimental to performance.

We are working in collaboration with a group at Arizona State University to form Josephson junctions by subtractive etching of the so-called “pentalayers.” A pentalayer covers an entire 4” silicon wafer and has the thin film form Nb/NbTiN/TaN/NbTiN/Nb, in which the TaN layer is the junction barrier. In varying the nitrogen content in TaN, the resistivity passes through the metal-insulator transition. By judicious choice of barrier thickness and resistivity, we can control the junction current density and shape of its I-V characteristic.

The experimental results are extremely encouraging. The I-V characteristics show a typical resistively shunted junction behavior. Critical current density of about 20 kA/cm2 has been obtained. This value is close to the desired critical current density for niobium-based junctions. Also, the correlation between the barrier resistance and the critical current has been observed. A parameter that determines the upper speed of superconducting SFQ digital circuit is the product (IcR) of the maximum zero-voltage current Ic and junction resistance R in the absence of supercurrent. We have obtained IcR products that will allow circuit operation at over 100 GHz and are quite similar to junction with such ideal properties. Our current effort is focused on optimizing the deposition parameters of barrier TaN and improving the reproducibility of junctions. The next step will be directed toward demonstrating various circuits using this new technology.

1Staff
2Staff

Send mail to the author : (xianghui@eecs.berkeley.edu)

Light-Anodization Process for High-Jc Micron and Submicron Superconducting Junction and Integrated Circuit Fabrication

Xiaofan Meng1 and Xianghui Zeng2
(Professor Theodore Van Duzer)
(ONR) N00014-00-1-0003

Superconducting devices have a very high operation speed (up to a few hundred GHz) and extremely low power dissipation, which are essential for ultra-high-speed computing and telecommunication applications. High switch speed requires high Jc (critical current density) of 10-20 kA/cm2 and small junction area (1 mm2 or less). Most current superconducting junction and IC fabrication is still based on 2-3 mm technologies. It is important for high-speed superconducting digital applications to develop a suitable technology for micron and submicron junction and IC fabrication. When the junction areas approach micron and submicron sizes, the fabrication becomes more difficult. For 1 mm2 junction, the via through the dielectric layer to contact the junction would have to be 0.6 mm2 or less. This would require advanced photolithography tools to increase resolution and alignment accuracy. It also demands better dry-etch profile control. One common approach is to use CMP to remove the covering dielectric layer and expose the underlying metal contact. But CMP complicates the process and increases the cost. We have developed a new approach for high critical current density (Jc) small junction fabrication. The key step is light anodization that forms a thin double-layer of Al2O3/Nb2O5 oxides around the junction area and on the sidewalls of the junction. This anodization ring is a good dry-etch stop, so the via for the junction contact can be larger than the junction area. The anodization ring can also protect the junction from plasma damage during dry etching and sputtering steps, therefore, it can reduce the junction leakage current and critical-current spread. The new technique is very simple and cost effective compared with the CMP approach. It needs only one additional mask and process step. We have used the technique to fabricate high-Jc submicron Nb/Al-AlOx/Nb tunnel junctions with very low critical-current spreads. The smallest junction area is 0.3 mm2. The critical current densities are up to 20 kA/cm2. Using this technique, we have also fabricated Nb SQUIDs and various Nb digital ICs. MIT Lincoln Laboratory, Hypres, and TRW have successfully adopted the new technique in their superconducting IC processes.

1Staff
2Staff

Send mail to the author : (meng@eecs.berkeley.edu)