Transistor scaling below 50 nm gate lengths will likely require the incorporation of new device structures in order to adequately control short-channel effects. A promising candidate is the FinFET, a double-gate MOSFET structure [1,2]. The device consists of self-aligned double gates surrounding a thin silicon slab (the “fin”), which can sufficiently suppress short-channel effects.
Thus far, device fabrication has taken place in a research environment and can consequently make use of non-standard tools such as electron beam lithography. In this work, a manufacturable FinFET process is developed using standard processing tools found in an industrial fabrication facility. Critical process steps have been evaluated using short-loop experiments, and initial device results have been obtained. Working transistors down to 10 nm in gate length have been successfully fabricated. Continued work will focus on achieving appropriate threshold voltages in order to study circuit performance.
One of technological challenges for thin body MOSFETs is threshold voltage (Vt) control. Ideally, the FinFET body should be lightly doped in order to achieve high carrier mobility for high transistor drive current, as well as immunity to dopant-fluctuation-induced variations in Vt. The required range of gate work functions for a fully-depleted CMOS FinFET technology is 4.4 V (NMOS) ~ 5.0 V (PMOS), which precludes poly-Si as a gate material. A metal gate with a tunable technology and dual gate work function was announced [1-4]. However, manufacturability and reliability of a gate dielectric should be considered for implementation of metal gate technology to FinFETs.
In this work, molybdenum (Mo) will be used for PMOS and Mo2N will be used for NMOS gate material after selective nitrogen implantation and annealing. Multiple threshold voltages can be achieved by changing a dosage of nitrogen. As an alternative, separated double gates at narrow silicon fins will be formed by chemical-mechanical polishing. Threshold voltages can be adjusted by different gate biases at both gates.
Semiconductor memories such as DRAM play an increasingly important part in determining the performance of microelectronic products. Their role has raised the demand for reliable, high density memories with fast data access and low power consumption. However, significant challenges must be overcome in scaling DRAM. Reducing the transistor's off-state leakage, for example, can require high substrate doping to sustain a large threshold voltage. Unfortunately, this approach enhances trap-assisted tunneling and leads to tail bits with small retention times. Another problem is the integration of a small storage capacitor in a technology which should provide an adequate sensing signal margin, long retention time, and soft error protection. As a result, it is unclear if DRAM can scale below feature sizes of 100 nm without changes in the standard 1 transistor/1 capacitor (1T/1C) cell design.
In this study, we investigate three new approaches at scaling DRAM. First, double-gate DRAM (DG-DRAM) is a new memory technology which embodies a thin body, double-gate structure. Scalability is intrinsic to its unique, compact design. We have compared DG-DRAM against other capacitorless DRAM technologies, considered variations in its cell design, performed experimental and simulation measurements, and explored soft error problems. In addition, two other capacitorless memory concepts are investigated. These include an improved version of a direct tunneling floating gate device, featuring a large threshold voltage window and superior data retention. A new direct tunneling, trap-based memory technology is also developed using conventional CMOS materials. These ideas represent novel and manufacturable approaches at bridging the gap between current CMOS memories and future technologies.
Controllability of off-state leakage current, with retention of large on-state drive current, is the primary challenge for scaling complementary metal oxide semiconductor (CMOS) transistor gate lengths into the nanoscale regime. Fully depleted ultra-thin-body (UTB) SOI metal oxide semiconductor field effect transistor (MOSFET) structures provide excellent suppression of short channel effects and performance improvement, and hence are promising for sub-70 nm CMOS technology . In order to avoid mobility degradation and threshold-voltage (VT) variation due to channel dopant fluctuations, it is desirable to use an undoped or very lightly doped (<1017 cm-3) silicon body. In this case, VT adjustment must be achieved by gate work function engineering, in the range from 4.4-5.0 V for a fully depleted SOI CMOS technology . Ideally, the technique for adjusting the gate work function should not utilize common dopants in Si, in order to avoid problems due to dopant penetration through ultra-thin gate dielectrics during the source/drain (S/D) annealing step(s). These requirements essentially rule out polycrystalline silicon (poly-Si) as a candidate gate material for nanoscale UTB SOI CMOSFETs. For simplicity of process integration, it is preferable to deposit a single gate material and subsequently adjust its work function selectively (e.g., in the n-channel vs. p-channel regions) as required. Molybdenum (Mo) is applied as the gate material to achieve the proper VT (-0.2 V) in p-channel UTB SOI MOSFETs for the first time, and VT adjustment via nitrogen implantation is demonstrated. Continued work will focus on investigating the statistical variation of the threshold voltage due to the nitrogen implantation and achieving appropriate threshold voltages with high-K dielectric (HfO2).
Monolithic integration of MEMS devices with driving and controlling electronics is advantageous for improving performance and potentially lowering cost. Polycrystalline silicon-germanium (poly-Si(l-x)Ge(x), where x is between 0 and 1), which has mechanical and electrical properties similar to poly-Si, is a promising candidate for the structural-layer material of post-CMOS integration of MEMS because poly-SiGe can be deposited (and annealed, if necessary) at much lower temperatures than poly-Si. To be successfully integrated with state-of-the-art electronics fabricated by IC foundries, any post-CMOS MEMS process with temperature higher than 450°C must be avoided.
While low-resistivity poly-SiGe can be easily obtained utilizing in situ p-type (i.e., boron) doping during deposition, poly-SiGe films as-deposited at 450°C or lower generally exhibit some level of residual stress and strain gradient. For optical switching/modulation and inertial-sensing applications, residual stress and strain gradient of the structural layers have to be minimized. From previous experimental results , it has been found that the stress and strain gradient of as-deposited poly-SiGe are dependent on deposition conditions, including temperature, pressure, and germanium content.
A full-factorial experiment was conducted to investigate the optimal deposition condition to achieve low stress and low strain gradient. Low residual stress (-9 MPa, compressive) and low strain gradient (2.4E-5µm-1) was achieved in as-deposited 2 µm poly-Si0.4Ge0.6 film deposited at 450°C and 600 mT. The residual stress and strain gradient were each generally found to increase significantly with decreasing deposition temperature. A 2 µm poly-Si0.4Ge0.6 film deposited at 425°C exhibited -45 MPa stress and 3E-4µm-1 strain gradient.
To further bring down the effective strain gradient, a bi-layer approach is currently under investigation. By depositing film with compressive stress on top of film with tensile stress, a bending-down moment can be created to cancel out the bending-up moment in general as-deposited films. Stress cancellation between two layers can also further lower the effective residual stress.
HfO2 is one of the most promising candidates to replace SiO2 as the gate dielectric because of its high permittivity, thermodynamic stability, and large energy-bandgap offset to Si. For simplicity of process integration, polycrystalline silicon (poly-Si) is preferred as a gate electrode material. However, the growth of an interfacial layer at the surface of the silicon upon high-temperature annealing (e.g., used for source/drain formation) increases the equivalent oxide thickness (EOT) and gate leakage current .
Polycrystalline silicon-germanium (poly-SiGe) has received much attention as an alternative gate-electrode material, because it alleviates gate depletion and boron penetration issues . Recently, it was reported that the use of poly-SiGe results in thinner EOT for HfO2 gate dielectric .
We investigate the mechanism responsible for this effect. Using MOS capacitors, the effect of the gate material and gate deposition rate on interfacial layer formation is studied. A conventional LPCVD furnace was used to deposit the gate materials (poly-Si and poly-Si0.8Ge0.2) at 550°C onto PVD HfO2 gate dielectric. The effect of gate deposition rate was studied by comparing the results for poly-Si deposited using SiH4 against those for poly-Si deposited using Si2H6. (The deposition rate for poly-Si using Si2H6 is about 8 times faster than that for poly-Si using SiH4; the deposition rate for Si0.8Ge0.2 is about 7 times faster than that for poly-Si using SiH4).
In a conventional CMOS process, polycrystalline-silicon doped heavily by ion implantation is used as the gate material. Thermal annealing (either in a furnace or rapid thermal annealer) is carried out to activate the dopants. However, due to the non-uniform implanted dopant profile and thermal budget constraints, it is difficult to achieve very high active dopant concentration (>10E20 cm-3) at the gate/dielectric interface. As a result, the lower portion of the gate electrode is depleted when the MOSFET is turned on, effectively increasing the thickness of the gate dielectric and thereby degrading the transistor drive current. The gate-depletion problem becomes significant as the equivalent oxide thickness (EOT) is scaled below 2 nm and the power-supply voltage is reduced to 1 V and below, and hence is a serious problem for sub-90 nm CMOS technologies.
In this project, pulsed (~30 ns) excimer laser (248 nm) annealing (ELA) is being investigated as a means to achieve high active dopant concentration with minimal thermal budget. The gate material is deposited in amorphous form (to provide a low melting temperature) and then implanted with dopants. An excimer laser pulse is then applied to momentarily melt the gate layer. In the melt, the dopants redistribute rapidly, resulting in a box-shaped concentration profile. The rapid cooling and crystallization process yields an active dopant concentration higher than the solid solubility limit. Thus, the gate depletion problem can be greatly alleviated.
Both n-channel and p-channel MOS devices will be fabricated using Si(1-x)Ge(x) (x=0, 0.2, or 0.4) as the gate material. The purpose of using a silicon-germanium alloy is to lower the gate melting temperature. (For example, the melting point of amorphous Si0.8Ge0.2 is estimated to be ~1000°C.) This may be needed in order for the ELA process to be used in conjunction with a high-permittivity gate dielectric material. The effect of ELA on gate sheet resistance, gate depletion, gate leakage, and gate-dielectric reliability will be monitored as a function of laser fluence for the various gate materials.
I propose that ultra-thin silicon nitride films be used to create abrupt junctions between n-type and p-type regions in microelectronic devices. These films should block unwanted boron diffusion. With a thickness of around 1 nm, the nitride layers should also be thin enough to allow charge carriers to tunnel through, thus causing minimal impact on electrical characteristics.
Two experimental stages will be necessary in order to determine whether silicon nitride can be a diffusion barrier to boron while allowing charge carriers to tunnel. First it will be necessary to find the fabrication parameters that will produce an ultra-thin silicon nitride film which blocks boron diffusion. Then it will be essential to optimize the electrical behavior of a device which has a nitride layer between its n- and p-regions.
Selective deposition of SiGe is advantageous for making a raised S/D FinFET with very low parasitic resistance, particularly needed for analog circuit applications. Ideally, the Ge content should be limited to less than 50% to simplify the S/D silicidation process. In this project, we will explore the use of Cl2 gas to enhance the selective deposition of low-Ge-content films on Si (vs. SiO2 or Si3N4) in a conventional LPCVD furnace. The chlorine is expected to promote selective deposition by removing ad-atoms on the insulator surface via SiCl2 or GeCl2 desorption, at temperatures above 700°or 400°, respectively. The gas flow ratios and process temperature will be optimized for high selectivity of deposition.
As the double-gate MOSFET (DG-MOSFET) structure is adopted for CMOS IC manufacturing in the sub-30 nm gate-length regime, the effects of process-induced variations on DG-MOSFET characteristics become very critical. In this research, we compare n-channel symmetric-double-gate (SDG) and asymmetric-double-gate (ADG) devices with nominal gate length of 9 nm in terms of their tolerance to process induced variations. The SDG device is assumed to have a gate material with work function 4.486 eV, while the ADG device is assumed to have n+/p+ poly-Si front-gate/back-gate. MEDICI device simulation is used, with a drift diffusion model for carrier transport and a realistic device structure based on ITRS specifications for the 9 nm technology generation. The results show that both ADG and SDG have acceptable performance within 25% bottom gate misalignment, 10% CD variation, and 5% Tsi variation. Thus, ADG and SDG are both fairly tolerant to process-induced variations. Quantum-confinement effects are more severe in the case of the ADG device and can be dominant for ultra-thin body thickness Tsi, however. Overall, the SDG structure seems to be more advantageous, which implies that metal gate technology will be needed to fully tap the circuit-performance benefits of the DG MOSFET structure.
Polycrystalline Silicon (Poly Si) has been commonly used for micro electromechanical systems (MEMS) applications, yet the main drawback of this material is that it requires a high processing temperature (higher than 800°C) in order to achieve the required mechanical properties. Such a temperature is too high when MEMS devices are fabricated after the electronics circuitry (especially if non refractory metals are used for CMOS back end technology). On the other hand, Poly-SiGe material has physical properties comparable to those of Poly-Si, yet it can be processed at low enough temperature to avoid damage on chips electronics. This makes Poly-SiGe very attractive for the integration of MEMS after standard electronics.
In order to achieve an optimal integration of MEMS devices with CMOS circuitry, the electrical connection between the MEMS and the electronics circuit needs to introduce the minimum possible interconnect parasitics. Therefore, direct deposition of SiGe onto metal is desirable. In addition, the specific contact resistivity between the two materials needs to be low enough, allowing it to be comparable to the state-of-the-art specific interconnect resistivity requirement (less than 1 ohm-cm2).
Using the well-known Kelvin structures, research of SiGe deposition on metal films is continuing with the prospect of determining the contact resistivity of p+ SiGe films deposited onto TiN of different contact area sizes. We are also interested to see how increasing or decreasing SiGe processing temperature (between 400°C and 450°C) affects the contact resistivity. The initial results obtained from the contact resistance measurements are very promising. Depending on the contact hole dimensions as well as the SiGe deposition temperature, it is possible to reduce the specific contact resistivity to less than 1 ohm-cm2. One of the main issues we've encountered is a proper cleaning process of the wafers prior to SiGe deposition. This is critical as it helps to achieve a good interface between SiGe and the metal film beneath, thus reducing the contact resistance. Using Argon Sputtering plasma rather than Helium plasma, we observed that the contact resistivity could also be reduced.
As the dimensions of semiconductor devices are scaled down in order to achieve higher levels of integration, optical lithography will no longer be sufficient for the needs of the semiconductor industry. There are some challenging issues with complicated mask technology and low throughput for some alternative lithography technologies such as X-ray, EUV, electron-beam lithography, etc. Focused ion beam (FIB) patterning of films is a well-established technique (e.g., for mask repair), but throughput has historically been a prohibitive issue in its application to lithographic processes in semiconductor manufacturing. The goal of this project is to develop a focused ion beam system for high-throughput resistless, direct patterning, and doping of films that can be made practical for high-volume production.
The compact FIB system being developed uses a multicusp plasma ion source and a novel electrostatic accelerator column. The multicusp plasma source can generate ion beams of various elements, such as O2+, BF2+, P+ etc., for surface modification and doping applications.
The beam brightness of a multicusp-plasma ion source has been substantially improved by optimizing the source configuration and extractor geometry. Measured beam brightness can be as high as 440 A/cm2Sr, which represents a 30 times improvement over previous work.
A multiple-beam system will be built by stacking multi-aperture electrode-insulator structure so that each beam is accelerated with the same electrode potentials. Parallel processing with multiple beams can greatly enhance the throughput of a FIB system.
We have investigated the process for direct patterning using focused O2+ ion beam. A thin surface oxide film on an Si wafer can be selectively formed using low energy focused O2+ ion beam. It can then serve as a hard mask for patterning of the Si film. We also investigated the formation of doped regions in bulk silicon wafers by scanning focused P+ beam implantation. To demonstrate the suitability of scanning FIB lithography for the manufacture of integrated circuits, the SOI MOSFET device fabrication using the process developed to pattern gate electrode and form source/drain region is in progress.
Double-gate (DG) MOSFETs are a proposed solution to extended CMOS scaling beyond bulk-Si MOSFETs. A variety of DG structures have been proposed . Vertical structures, such as the FinFET have a layout penalty related to the routing of wires to both the gates. A planar DG can be seen as a possible solution to such a problem. An experimental feasibility study for a self-aligned double gate structure has been proposed . In this present work, the work is being extended to produce sub 50 nm DG MOSFETs with Mo-gates to reduce gate depletion effects. Currently the feasibility of using such an approach for sub 50 nm DG structures is being investigated using a back-side illumination process on quartz substrates. After that, transistors will be fabricated using a similar approach. In parallel, simulation studies on device optimization are being pursued to optimize the circuit performance of DG MOSFETs.
The rapid growth of the semiconductor industry has been enabled by transistor scaling to improve the performance and cost of integrated circuit products. Continued scaling of the MOSFET presents new technological challenges as fundamental material and process limits are approached. It would therefore be useful to investigate novel FET structures that could be simpler to fabricate and more scalable than the MOSFET.
In this project we are focusing on the fabrication and characterization of short-channel (Lg < 20 nm) thin-body Schottky-gate transistors. The chief advantage of this structure compared to the conventional MOSFET lies in its extreme simplicity of structure and fabrication. The transistor has no p-n junctions between the S/D and channel, thus eliminating the requirement of hyper-abrupt junctions. The structure is constituted of a metal semiconductor contact as the front gate and a MOS back gate to adjust the threshold voltage. The conduction through the device is essentially resistive (similar to a JFET) with the resistance of the channel being adjusted using the front and back gate voltages. The channel lies in the middle of a thin silicon layer, thus making the interface quality unimportant for performance. In order to have channel pinch off at low gate voltages and good drive currents at high gate voltages of about 0.6 V (as desired for sub 10 nm devices), it is essential to have a heavily doped thin silicon channel, with the silicon thickness not very critical. Also, unlike the double gate MOSFET, the alignment between the front and back gates is not important for good transistor performance.
A metal-semiconductor contact typically suffers from (1) a large leakage current and, (2) Fermi level pinning. In order to overcome the two issues, an extremely thin layer (5-10 A) of silicon nitride is proposed to be used as a front gate dielectric. With conduction through the middle of the channel, the interface quality is not going to be very critical to the transistor performance. Simulations of this structure were done using the device simulator MEDICI and the results were compared to comparable double-gate MOSFET structures. The drive currents and short channel effects are comparable to the MOSFET, with the MESFET showing a better short channel performance. The drive current and transconductance are slightly poorer, but other benefits of the device are compelling enough to pursue the device further.
The fabrication of this structure has been started with the first run being tried on a poly-silicon channel to evaluate the feasibility of this idea. Later on, emphasis shall be given on thin silicon film crystallization to improve the transistor drive current. In the future we propose to demonstrate that this device can be scaled down far beyond the MOSFET limits and, theoretically, all the way to atomic dimensions. With a simple process flow and a poly-silicon channel, it is likely to be a good candidate for 3D intregration of devices as well.