This work relates the potential energy savings to the energy profile of a circuit. These savings are obtained by using gate sizing and supply voltage optimization to minimize energy consumption subject to a delay constraint [1,2]. The sensitivity of energy to delay is derived from a linear delay model extended to multiple supplies. The optimizations are applied to a range of examples that span typical circuit topologies including inverter chains, SRAM decoders, and adders. At a delay of 20% larger than the minimum, energy savings of 40% to 70% are possible, indicating that achieving peak performance is expensive in terms of energy. The analysis is extended to register files, minimizing energy across pipeline stages, and optimal parallelism.
In current attempts at low-power, single-chip, integrated radio solutions, the analog circuitry tends to consume a majority of the total power. Tight RF requirements on the front-end receivers, and large transmit powers necessary for long distances and high signal-to-noise ratios, constrain a design with difficult, if not impossible, specifications to implement in very low power in low-cost CMOS technology. While low-power digital techniques for large-scale designs exist and are being actively applied, no comparable techniques have emerged yet for the analog design components. Current trends suggest that the while the speed and energy efficiency of digital circuits will improve with the lower supplies and smaller geometries, analog circuits are actually hampered by the supply reduction. This suggests a sort of "Holy Grail" for radio design, which eliminates as much as possible the necessity for analog components. This radio would ideally convert the incoming antenna signal to a binary value and then perform all processing digitally, yielding an implementation with all of the benefits digital design has to offer (full integration, lower power, cheaper technology, robustness, the ability to implement complex algorithms such as adaptation, maximum likelihood estimation, etc.) While current radio standards would require a very fast and high accuracy A/D, we believe that by using a pulse-based, ultra-wideband (UWB) signaling scheme we can approach this fully-digital, fully-integrated radio; reducing both transmit power and the receiver's analog complexity beyond simply scaling a traditional narrowband transceiver.
The focus of this research is the design of such a "fully-digital" single-chip radio transceiver. We assume no special or fixed building infrastructure; the radios will be able to communicate flexibly in both peer-to-peer or broadcast modes. The target cell-size is approximately 5-10 meters with an estimated maximum of 32 active users at one time per cell. The anticipated bit-rate will be around 100 kb/s (uncoded BER ~1e-3) with a total 1 mW (TX+RX) power budget for the transceiver. A narrow pulse (approximately 1 ns wide) is transmitted using simple digital switches; spreading energy over a Gigahertz of bandwidth. Reception, after wideband gain and filtering, occurs in a bank of A/D converters which capture the received pulse in an adjustable window of 16 to 64 ns (shown in Figure 1). This window is composed of 32 to 128 data samples at a 2 GHz rate and is repeated at the pulse broadcast frequency which may range from 62.5 MHz to roughly 1 MHz. The digital backend (shown in Figure 2) aggregates these windows into a block of 256 samples which is fed into a bank of 128 parallel matched filters of length 128 samples each with 5-bit programmable taps. The outputs of these matched filters are sent to either an acquisition or synchronization block. The synchronization block implements early-late correlation for tracking, and the acquisition block contains 11 de-spreading correlators in parallel as a compromise between area and search time. Once a correlation peak above the programmable threshold is found by the peak detector logic, the backend switches from acquisition to tracking mode. For flexibility, separate spreading codes may be used for acquisition and synchronization and both may be of length 1 to 1024 chips.
In addition to communication, the ability to do some form of ranging or localization is a considered a necessity. Due to the fine time resolution inherent to UWB, accuracy on the order of several feet is possible and research into robust ranging algorithms has begun. Also, as extreme low cost and high integration are desired, we are investigating PCB/circuit co-design for the antenna and matching elements, and targeting a generic, digital CMOS IC process for fabrication.
Figure 1: Analog frontend block diagram
Figure 2: Digital backend block diagram
Microprocessors, both general purpose and application-specific, are inherently limited by a small amount of instruction-level parallelism (due to branches, precise interrupts, etc.) and increase in performance primarily through scaling of the core clock frequency. Although partially mitigated by improved process technologies, each increase in performance comes with a corresponding increase in power consumption.
This research will investigate hardware-based general purpose computing without any use of the von Neumann software architecture. The Berkeley href="http://bwrc.eecs.berkeley.edu">BWRC, will be used to develop the methodologies for computing purely with hardware and investigate how to maximally benefit from parallelism in the absence of a sequential instruction stream. Emphasis will be placed on translating the well-understood semantics of sequential programming (such as function libraries, processes/threads, and address spaces) into their corresponding constructs in hardware, as well as evaluating flexible and scalable computing fabrics (such as ALU meshes and neural networks) which map well into the incremental configuration features of FPGAs.
Because of the ultra-wide bandwidth of the transmitted signal, receiver design strategy has different interesting issues from narrowband systems. Given the fact that ultra wideband has several possible application areas, system-level explorations will be done in this research. Our first work will be focused on building a real-time Simulink model which includes both the analog and digital processing components in a UWB system. The simulation combined with the future UWB test board will allow us to understand more about system tradeoffs as a basis of future ultra wideband system design.
A digital back end with basic synchronization and tracking functionalities was first implemented via BEE emulation engine. With the help of FPGA testing, we could play with more sophisticated detection algorithm to improve the system performance from communication theory perspectives. An ASIC version of the baseband using the new design flow in BWRC will also be done in this project. The final goal of this project is to propose a suitable architecuture of UWB system operating between 3 GHz and 10 GHz.
Ultra-wideband (UWB), as opposed to traditional narrowband radios, is a wireless digital communication system that exchanges data using short duration pulses. The complexity of the analog front-end in UWB is drastically reduced due to its intrinsic baseband transmission. Based on this simplification and the high spreading gain it possesses, UWB promises low-cost implementation with fine time resolution and high throughput at short distances without interfering with other existing wireless communication systems. However, the wideband nature of the front-end architecture leads to a totally different design methodology from traditional narrow-band systems. For example, if one employed the conventional narrow-band design approach, matching between the power amplifier and the antenna would be a big problem owing to the fact that it is extremely difficult to match accurately over a such a wide range of frequencies. In addition, we desire a high degree of integration, which requires an antenna on the order of centimeters in size, but it is hard to attain efficient transmission bandwidth from DC to GHz with such a small antenna.
The focus of this research is to determine the methodology for co-designing an appropriate antenna suitable for efficient pulse transmission/generation and pulse reception with analog circuits that won’t induce signal dispersion (ISI, inter-symbol interference) or further complicate the digital back end. Finite-difference time-domain (FDTD) electromagnetic wave simulation will be used to characterize the antenna. While doing antenna/circuit co-design optimization, the method of combining FDTD and SPICE simulation will also be investigated.