Modern broadband communication systems require highly stable frequency references adjustable over a wide range of frequencies. One such system is a cable tuner, which requires a voltage-controlled oscillator (VCO) capable of tuning between 1.2 and 2.1 GHz and a phase noise below –85 dBc/Hz at a 10 kHz offset from the carrier . Solutions addressing such specifications have traditionally relied on expensive high-end technologies and external components . Today’s CMOS technologies are cost-effective and provide sufficient bandwidth for many RF communication applications. This research project focuses on the design of wideband low-phase-noise frequency VCOs in CMOS.
Although various types of VCOs can achieve a wide tuning range, LC VCOs are most suitable since they generally exhibit lower phase noise. To achieve a wide tuning range using a single resonator, we propose a VCO tuned using a mixed-signal scheme. Its frequency is digitally adjusted in coarse steps and subsequently fine-tuned to the desired value using a varactor device. An amplitude control scheme is also implemented.
The goal of this research project is to establish a framework for the analysis, design, and optimization of wideband low-phase-noise VCOs. Tradeoffs between different candidate LC VCO topologies and between available devices will be investigated. The effects of varactor nonlinearities on phase noise and tuning range will be analyzed. A set of analytical methods will be provided to aid in predicting these effects and any other quantities relevant to the overall VCO performance. Our proposed LC VCO will be integrated within a frequency synthesizer to demonstrate its practical feasibility.
One of the most important specifications in a wireless transmitter is the adjacent channel power ratio (ACPR), which is used to measure the nonlinear distortion in the transmitted signal. ACPR, together with the modulation scheme, determines the maximum allowable nonlinearity of the power amplifier, the last active circuit block before the antenna. Although other measures of distortion such as harmonic or intermodulation distortion have been analyzed before, the relationship between the physical mechanisms in the transistors and ACPR is not well understood. Designers are also hampered by the difficulty of simulating ACPR, as carrier frequencies are often two orders of magnitude higher than the channel bandwidth.
In this research project, we will try to predict ACPR in linear RF power amplifiers required in wireless systems using non-constant envelope modulation schemes, such as CDMA. At first, frequency domain Volterra kernels will be calculated to model the nonlinear behavior of the power amplifier. Then the baseband equivalent of the transmitted signal will be fed into this model in order to estimate ACPR using MATLAB. As all of the simulations will be done in the frequency domain, the simulations are not expected to take long. This method can easily be used for processes from different vendors, once the basic SPICE parameters are known. Besides, it will also help designers during the initial design phase, because it does not require any amplifier to be fabricated and measured beforehand, as opposed to the empirical methods that utilize some form of parameter fitting. Vendors can also modify their processes to design special transistors for power amplifiers, once the main contributors to distortion and tradeoffs are identified.
The accuracy of this method will be tested by making measurements on single and two stage SiGe bipolar power amplifiers designed and fabricated using a commercially available BiCMOS process from Maxim Integrated Products. The measurements will be made using the IEEE 802.11b standard which operates at a 2.4 GHz ISM band.
Modern cable and wireless communication systems require gain control in the signal path. For example, a CDMA phone needs adequate control of its output power in order to maintain an efficient link between the user and the base station. Depending on the distance between the receiver and the base station, the received power may vary by orders of magnitude. Hence, gain control circuitry is needed to limit the incident power to the receiver chain. Therefore, much effort has been put into the design of attenuators that can be used as a means of controlling the received signal strength.
Attenuators with a broad response are desirable since they can be used in applications operating over different frequency bands. There are two main methods to build broadband attenuators. PIN diode attenuators have been used for this purpose. Although they are very linear, broadband, and able to handle high power, their main drawbacks are constant power dissipation and difficulty in integrating them on-chip. FET's ability to be used as a voltage controlled variable resistor in the triode region makes them another suitable choice in the design of attenuators. GaAs MESFETs have been the traditional choice in the design of attenuators due to their superior high-frequency performance compared to MOSFETs. However, the low cost and availability of CMOS makes it an attractive choice of technology for attenuator design. Furthermore, the downscaling of CMOS technology continues to provide transistors with higher fTs, which are more suitable for broadband RF-IF attenuators.
The goal of this research project is to analyze and design broadband CMOS attenuators, which can be integrated on-chip. The focus will be on possible advancements in the design of attenuators on the circuit level as well as on the device level. Device and circuit optimization will be studied for distortion, frequency response, power-handling capability, and insertion loss. Gain control circuitry will be designed for linear attenuation with the control voltage. Various attenuator ICs will be designed and tested for verification of the analysis.
The simplicity of the direct conversion receiver offers some important advantages over the superheterodyne architecture. The RF signal is filtered, amplified, and then converted to baseband directly. There is no IF signal, and hence the image reject filter, IF amplifier, and high-Q IF channel select filter are no longer required. Without these components, the homodyne receiver can achieve a higher level of integration than the heterodyne counterpart, and integration can translate into cost savings.
However, the direct conversion architecture also has some disadvantages that make its implementation difficult. DC offsets, 1/f noise, and second-order distortion from the mixer will all fall in the signal band. Another problem is LO self-mixing. Since the RF and LO are at the same frequency, any leakage from the LO port to the input of the mixer is going to produce a DC component at the output, adding to the DC-offset problem.
The goal of this project is to study the use of sub-harmonic mixers in the direct conversion receiver. Because the LO is now at a fraction of the RF frequency, any LO leakage to the input of the mixer will be mixed to a frequency outside the signal band. Currently, a sub-harmonic mixer in a 0.13-µm CMOS process is being designed.