This project will investigate the possibilities of using digital signal processing techniques to enhance pipelined A/D converter performance. Specifically, we're currently applying the Wiener filtering concept to the correction of analog errors. With a slow-but-accurate helper A/D and a back end FIR digital filter, we have proven in simulation that capacitor mismatch, finite opamp gain, and various offset errors can be eliminated through the digital filtering. The analog signal paths involved are open-loop. Correction is performed solely in digital, without feedback to the pipeline A/D to tweak analog parameters. The system is further made adaptive to track slow environmental changes (power supply voltage drift, ambient temperature change, etc.) by means of an LMS algorithm. Adaptation rate can be adjusted depending on the speed of the slow helper. With this approach, we're potentially looking at a very high conversion speed (> 200 MS/s) and high accuracy (>= 10 bits) where the stringent requirement on analog circuit components can be relaxed with the aid of digital techniques. Down the road, we will also investigate applications of Voterra filtering to correct nonlinearities and bandwidth limitations in analog circuits where the complexity of digital filters will increase geometrically. The driving force behind this, however, is the inexorable power of scaling coming from digital CMOS technology. If strategically leveraged upon, it will revolutionize the performance and design of traditional analog circuits in the near future.
The 4G Wireless LAN demands a high data rate, such as multi-gigabits/s. The need for such a high data rate Wireless LAN has prompted the Federal Communications Commission (FCC) to release 5 GHz of unlicensed spectrum, from 59 GHz to 64 GHz.
In 60 GHz radio systems, there is not only a high frequency operation issue but also a baseband processing issue. In the case that we operate five channels in a 5 GHz band, one channel of bandwidth is 1 GHz. In order to process a 1 GHz bandwidth channel, we need a 4 GS/s A/D converter, which doesn't bode well either in the realization of such an A/D converter or in the digital signal processing after A/D conversion.
One of the conventional approaches for meeting the high-speed requirement is a time-interleaved parallel A/D converter. At the sampling rate of 4 GS/s, it suffers from path mismatch, marring system performance, and adds the complexity of digital error calibration. Even after A/D conversion, the digital signal processing speed is still 4 GHz.
One of the promising communication modulation schemes for wideband applications is orthogonal frequency division multiplexing (OFDM). OFDM consists of multiple subcarriers, and each subcarrier is orthogonal to the other subcarriers. 60 GHz radio systems consider OFDM to be the strong candidate for the modulation schemes. The new idea came from the unique characteristics of OFDM.
The key idea of parallel path receiver architecture is that a wideband OFDM channel can be split up into a number of uncorrelated narrow band OFDM subchannels. For example, a 1 GHz channel has 200 MHz of guard band and 800 MHz of information channel with 1024 OFDM subcarriers. When we split up the 800 MHz bandwidth channel into 8 subchannels, each subchannel has 100 MHz bandwidth with 128 OFDM subcarriers. We just need to process 100 MHz of bandwidth with 400 MS/s A/D converter, but we need to have eight copies of the same blocks. This approach doesn't suffer from the path mismatch problem. 400 MS/s A/D converter is easy to design and the digital signal processing can be run with 400 MHz, which implies a low energy solution.
From the circuit design perspective, the important circuit building blocks are mixers and frequency synthesizers, because they are sensitive to cross talks. Parallel mixers are exposed to the possible cross modulation. Frequency synthesizers are vulnerable to the cross harmonics. This research project places emphasis on the demonstration of parallel mixers and frequency synthesizers operating against two cross talks. Another issue is the reasonable power consumption for the parallel mixers and multiple frequency synthesizers.
The test structure of mixers and frequency synthesizers will be designed with 0.13 µm CMOS. There are four parallel paths. The operating intermediate frequency is 2.5 GHz. The subchannel bandwidth is 50 MHz. The circuit topology of mixers is a parallel folded active mixer with current bleeding. This topology reduces the effective input loading and power consumption of parallel mixers and isolates the cross modulation. The circuit topology of frequency synthesizers is a mixer-based frequency synthesizer, which eliminates the frequency divider.
Steady trends in the personal portable communications market have demanded lower cost and better overall performance of the transceiver. Modern CMOS technologies, currently demonstrated to be feasible for implementing RF circuitry, offer the prospect of higher levels of integration, bringing low cost, smaller form factors and, with the elimination of many off-chip signal paths, the potential for reduced power consumption. At the system level, non-constant-envelope (non-CE) modulation schemes are attractive, as they offer better spectral efficiency than CE schemes, allowing higher data rates to be transmitted in a given bandwidth. The goal of this work is the design of an integrated CMOS radio transmitter for a non-CE modulation scheme.
Battery life is a major consideration in the design of portable radio units, and this is particularly so in the design of the RF power amplifier with its significant power consumption. At the same time, non-CE modulations require a linear transmit path for low distortion, and there exists a fundamental tradeoff between linearity and power efficiency, and CMOS device characteristics only make this tradeoff worse.
Cartesian feedback is a linearization architecture that can provide a low-distortion output from a nonlinear amplifier, offering the potential for integration without needing off-chip delay lines or couplers. This architecture requires a power amplifier whose output envelope can be modulated by varying the input envelope. Though Class-C power amplifiers allow this modulation, while offering good power efficiency, they also have bad AM/PM distortion, which can introduce instability with Cartesian feedback.
We are investigating a modification to the normal class-C amplifier architecture to reduce the severity of AM/PM distortion. Simulated peak drain efficiencies for a 0.18 Ám CMOS prototype amplifier are on the order of 55%. The larger goal of this work is to implement this modification together with the other elements of the Cartesian feedback architecture in an integrated transmitter targeting GSM EDGE specifications.
In many portable transceivers, the power amplifier (PA) is the most power consuming block. In general, the maximum power efficiency can be achieved only when the PA is transmitting peak output power. The efficiency worsens as the output power decreases. Under typical operating conditions, the PA transmits less than peak output power, therefore effective power efficiency is much lower than the maximum value.
One of the efficiency enhancement techniques under investigation is the Doherty amplifier. The merit of this technique is that it allows a power amplifier to achieve a maximum or close-to-maximum efficiency over a wider range of the output power. In the Doherty amplifier, an auxiliary amplifier is introduced. The auxiliary amplifier turns on when the output power is high and, by means of a passive impedance inverter, effectively lowers the impedance seen by the main amplifier, thus allowing higher output power while maintaining high efficiency. However, since the Doherty amplifier consists of two amplifiers, it is subject to phase mismatch between the two paths. Also, the main amplifier has to experience different load impedance due to the on and off state of the auxiliary amplifier. These can lead to a significant degradation in the linearity. Different linearization techniques that can be applied to Doherty amplifier will also be investigated.
The great success of the digital CMOS IC technology during the last ten years has firmly built up the dominance of CMOS as the mainstream silicon technology of the IC industry. The everlasting pursuit for high integration and low cost has also endorsed the design methodology known as the "system-on-chip" approach. But integrating noise-sensitive, high-sensitivity analog and RF circuits on the same die with noisy digital signal processing (DSP) circuits switching at high frequencies is a very challenging task for circuit designers. The demand for wide bandwidth of the analog front-end exacerbates the problem since the designer cannot benefit from most of the narrow-band techniques, such as noise shaping and filtering. This underlines the need for innovation of broadband, power-efficient analog circuit techniques that also feature high dynamic range.
Among these challenges, the analog-to-digital interface circuit is one of the most difficult to deal with and can often consume 50% of the total receiver power. This underlines the research effort for innovations of analog circuit techniques in the deep-submicron regime. This research project will investigate these limitations and propose new techniques that ameliorate strong tradeoffs among power, accuracy, and bandwidth of the A/D interface circuits.