Abstracts for Jeffrey Bokor

The EECS Research Summary for 2003

Industrial FinFET Fabrication Using Standard Processing Tools

Leland Chang
(Professors Jeffrey Bokor, Chenming Hu, and Tsu-Jae King)
(SRC) 850.002

Transistor scaling below 50 nm gate lengths will likely require the incorporation of new device structures in order to adequately control short-channel effects. A promising candidate is the FinFET, a double-gate MOSFET structure [1,2]. The device consists of self-aligned double gates surrounding a thin silicon slab (the “fin”), which can sufficiently suppress short-channel effects.

Thus far, device fabrication has taken place in a research environment and can consequently make use of non-standard tools such as electron beam lithography. In this work, a manufacturable FinFET process is developed using standard processing tools found in an industrial fabrication facility. Critical process steps have been evaluated using short-loop experiments, and initial device results have been obtained. Working transistors down to 10 nm in gate length have been successfully fabricated. Continued work will focus on achieving appropriate threshold voltages in order to study circuit performance.

X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub 50-nm FinFET: PMOS,” Int. Electron Devices Mtg., Washington, DC, December 1999.
Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET Process Technology for Nanoscale CMOS,” Int. Electron Devices Mtg., Washington, DC, December 2001.

Send mail to the author : (leland@eecs.berkeley.edu)

Threshold Voltage Control at Double-Gate Devices

Yang-Kyu Choi1
(Professors Jeffrey Bokor and Tsu-Jae King)
(MARCO) 2001-MT-887 and (SRC) 2000-NJ-850

One of technological challenges for thin body MOSFETs is threshold voltage (Vt) control. Ideally, the FinFET body should be lightly doped in order to achieve high carrier mobility for high transistor drive current, as well as immunity to dopant-fluctuation-induced variations in Vt. The required range of gate work functions for a fully-depleted CMOS FinFET technology is 4.4 V (NMOS) ~ 5.0 V (PMOS), which precludes poly-Si as a gate material. A metal gate with a tunable technology and dual gate work function was announced [1-4]. However, manufacturability and reliability of a gate dielectric should be considered for implementation of metal gate technology to FinFETs.

In this work, molybdenum (Mo) will be used for PMOS and Mo2N will be used for NMOS gate material after selective nitrogen implantation and annealing. Multiple threshold voltages can be achieved by changing a dosage of nitrogen. As an alternative, separated double gates at narrow silicon fins will be formed by chemical-mechanical polishing. Threshold voltages can be adjusted by different gate biases at both gates.

I. Polishchuk, P. Ranade, T.-J. King, and C. Hu, "Dual Work Function Metal Gate CMOS Technology Using Metal Interdiffusion," IEEE Electron Device Lett., Vol. 22, 2001.
Q. Lu, R. Lin, P. Ranade, T.-J. King, and C. Hu, "Metal Gate Work Function Adjustment for Future CMOS Technology," Symp. VLSI Technology, Kyoto, Japan, June 2001.
R. Lin, Q. Lu, P. Ranade, T.-J. King, and C. Hu, "An Adjustable Work Function Technology Using Mo Gate for CMOS Devices," IEEE Electron Device Lett.,, Vol. 23, 2002.
M. Qin, V. M. C. Poon, and S. C. H. Ho, "Investigation of Polycrystalline Nickel Silicide Films as a Gate Material," J. Electrochemical Society, Vol. 148, 2001.
1Postdoctoral Researcher

Send mail to the author : (ykchoi@eecs.berkeley.edu)

Advanced EUV Imaging*

Michael D. Shumway
(Professor Jeffrey Bokor)
(DARPA) MDA972-97-1-0010 and (SRC) 96-LC-460

Extreme ultraviolet (EUV) projection lithography is a proposed next-generation lithography technique for manufacturing integrated circuits at high volumes. It is targeted to print critical dimensions of 70 nm and below with a large depth of focus. An EUV microstepper using a 10x Schwarzschild objective is currently in use through modifications of an EUV PS/PDI station (phase-shifting/point diffraction interferometer). This EUV interferometer is located at the Advanced Light Source undulator beamline 12.0.1 (Lawrence Berkeley National Laboratory).

To evaluate resist materials for EUV lithography, it is necessary to expose test patterns with very high spatial resolution (less than 50 nm lines and spaces). Currently, there are a limited number of imaging systems that can achieve this fine feature printing at EUV wavelengths. By developing this synchrotron-based imager using the 10x reduction Schwarzschild optics system, the limits of test resists can be examined. One method to print these fine features is to double the spatial frequency of the object grating.

Placing a grating in the path of the coherent EUV source will create diffracted orders at angles determined by the pitch of the grating. By eliminating the DC term and recombining only the +1 and -1 orders, spatial frequency doubling at the image plane can be achieved with high contrast. The combination of the frequency doubling and the optical system creates a 20x reduction of the object grating pitch. Thus far, we have successfully used this technique to print equal line and space patterns with line widths as small as 30 nm. Line edge roughness measurements have been done on our 50 nm dense lines/space pattern with a three sigma rms value of 4 nm. The printing of even smaller features is currently under investigation. Simulations show that by using the fully extended NA, the system can achieve line widths as small as 12 nm. Using a suitably designed mask, spatially separate grating objects with differing pitch can be simultaneously imaged in a single exposure. A technique to print multiple contrasts during a single exposure is also being developed. These configurations will be of great use in evaluating the ultimate performance and extendibility of resist materials for EUV lithography.

More information (http://www.cs.berkeley.edu/projects/bokorgroup) or

Send mail to the author : (shumway@eecs.berkeley.edu)

Scanning Microscopy Probe for Nanomechanical Resonators

MinCheol Park1 and Xuchun Liu2
(Professor Jeffrey Bokor)

The goal of this project is to extend the probe technique by combining it with optical excitation to characterize the nanomechanical resonators without electrical drive structures.

1Postdoctoral Researcher
2Graduate Student (non-EECS), UC Davis

Send mail to the author : (jhuggins@eecs.berkeley.edu)

Sub 30 nm MOSFET Fabrication

Peiqi Xuan
(Professor Jeffrey Bokor)
(MARCO) 2001-MT-887

A thin body (<10 nm) is essential for sub 50 nm MOSFETs. Our work with the planarized solid-phase epitaxy process succeeded in 2000. This year we will use a dummy layer on the SPE film to improve the crystalline quality of the channel. After selectively removing the dummy layer, we can get excellent channel film while keeping its ultra-thin thickness. Better device performance is expected from this new fabrication technique.

Besides the process difficulties associated with the ultra-thin body, the control of the threshold voltage becomes a big issue for ultra-thin body devices, because the body doping is not effective in tuning the threshold voltage. Gate work function is believed to be the only method for the right Vt. Various metal gates and silicide gates are going to be tested for the right work function and CMOS process compatibility. Silicide gate with various types of doping shows a continuous range of work function, which makes the material perfect as a gate. With the primitive result we have, silicide gate covers the work function range required by UTB and FinFET devices. Fabrication is in progress.

An analytical model for fully depleted thin SOI and double gate MOSFET is also in progress. We solve the Poisson equation in the thin body and can calculate the 2D potential profile. We investigate the effect of the high k dielectric and pocket doping. We can use the analytical results as a guide for device designing, incluing the device dimensions and doping profile.

P. Xuan, J. Hedzierski, V. Subramanian, J. Bokor, T.-J. King, and C. Hu, "60 nm Planarized Ultra-thin Body Solid Phase Epitaxy MOSFETs," Device Research Conf., Denver, CO, June 2000.

Send mail to the author : (xuanpq@eecs.berkeley.edu)

Study of the Effects of Process Variation in Affecting the Performance of Nano MOSFET Devices

Shiying Xiong
(Professor Jeffrey Bokor)
Smart Project (SFR)

Gate line edge roughness (LER) is the random deviation of gate line edges from an ideal definition. It can be produced in lithography and etching steps. LER does not scale down with line width and only reduces with improved process conditions. Recently, as the industry is pushing their logic development toward sub-50 nm physical gate lengths, gate LER is an increasing concern, for it potentially affects circuit performance and reliability. The LER effects on MOSFET device performance have been studied by us and several other research groups through device simulation. In cooperation with AMD, we also performed an experimental study of the effects of gate line edge roughness on the electrical characteristics of bulk MOSFET devices. The physical gate length of the devices ranged from 0.76 µm to 30 nm. Pronounced difference of the gate line edge roughness was introduced using special lithographical techniques. Poly gate LER was characterized with SEM in an approach we developed. In electrical characterization, we compared device data with different gate line edge roughness. We studied the yield, threshold voltages, and DIBL as well as the current universal curves of both NMOS and PMOS devices. The detailed results will be reported in our publication.

As the gate length of MOSFET devices shrinks down below 20 nm, double-gate device structures are emerging as a strong candidate, even considering the added process complexity. This is because double-gate structures have better control of the short channel effect and near ideal turn-off slope. A much lower leakage level can be maintained even with very small gate length. The FINFET device, which is a vertical double-gate MOSFET, has demonstrated such potential capability experimentally. Using device simulations, we have investigated the effects of process variations on the electrical behaviors of 20 nm symmetric double-gate MOSFET devices designed for low power application. First, we studied the effect of doping profile fluctuation. Double-gate devices with poly silicon gates must have very high channel doping in order to reach the desired threshold voltage. In this case, we find the 3s value of VT variation caused by random impurity placement could be very large. This confirmed the effort of our group to engineer the work function of gate materials and maintain low or intrinsic channel doping in FINFET devices. Second, based on the device design with intrinsic channel and ideal gate work function, we analyzed the change of device electrical parameters caused by the variations on physical parameters such as gate length, body thickness, and gate dielectric thickness. We found that quantum effect has great impact on the performance of devices at this scale. The device electrical behavior is most sensitive to small variations in body thickness while the variations of effective channel length and other physical parameters are less critical. Based on these results, we gave predictive estimation on the tolerance of the device to different process variations in circuit application.

I am also targeting to study the effect of process variation on circuit performance and carrier transport in the channel of FINFET devices. I will devote my research to developing techniques and collecting experimental data in this study.

Send mail to the author : (xiongsy@eecs.berkeley.edu)

Scanning Microscopy Probe for Nanomechanical Resonators*

Xuchun Liu1
(Professor Jeffrey Bokor)
Integrated Microwatt Transceivers

This project is one part of a large project named Integrated Microwatt Transceivers launched this summer at BSAC at UC Berkeley. The aim of the whole project is to do the research on the architecture, circuit design, and fabrication technologies for integrated transceivers that exploit the analog signal processing capabilities of banks of nanomechanical filters. The requirements for the nanomechanical filter banks are to have an insertion loss of less than a few dB and a Q on the order of 10,000 in the carrier frequency range, which is 1-2 GHz in the near term and 5-10 GHz or higher in the future wireless sensor networks. The purpose of our project is to characterize the nanomechanical resonators by interferometer or atomic force microscope (AFM) combined with optical actuation.The result we got so far is the measurement by AFM of the out-of-plane movement of the film bulk acoustic resonator (FBAR) around its resonant frequency, i.e., 1.96 GHz.

Figure 1: Picture of the AFM setup
1Graduate Student (non-EECS), Cornell University

Send mail to the author : (xuliu@eecs.berkeley.edu)

Maskless Lithography with Nanodroplets

Yan Wang
(Professor Jeffrey Bokor)
(DARPA) MDA972-97-1-0010 and (SRC) 96-LC-460

Applying drop-on-demand (DOD) inkjet printing technology to directly write photoresist or polymer patterns on a wafer surface is becoming a new and powerful tool for microprocessing. Compared with other lithography approaches, this maskless lithography method has the advantages of the low cost, the wide variety of materials it could pattern, as well as the versatility of the substrates that a circuit could be built on.

The existing inkjet systems could only form liquid droplets with a volume bigger than several picoliters, which limited their minimum printable size to tens of microns. To build a system that is capable of producing droplets in the micron to submicron regime, we first chose a thermal bi-membrane actuator structure to provide the high driving force for ejecting a small droplet. However, the bi-membrane system suffered problems such as fragility of the membranes and irregularity of droplet generation. Therefore, we rebuilt our system based on the most common actuation mechanism used nowadays in inkjet printers–thermal vapor bubble formation by applying an extremely high thermal flux to the liquid on top of a smooth heater surface. The pressure change generated by the rapid growth and collapse of a vapor bubble in a chamber will push liquid through a nozzle and then break it to form a single droplet.

We have been able to successfully fabricate monolithic thermal bubble inkjet printheads by epoxy stamp bonding, in which we bonded a pair of wafers with nozzle, chamber, and heater structures using a thin film of epoxy transferred to the high areas of the top wafer by a dummy. The test chips were then plugged into our experimental system (as described in abstracts in previous Research Summaries) and we observed stable and continuous generation of 13 µm scale water droplets from those chips (Figure 1). Our next step is to shrink the liquid size further by reducing the nozzle diameter and changing the electric driving conditions. We will also try to print patterns with different materials utilizing the new printhead.

Figure 1: Water droplets generation sequence viewed at the nozzle of our new monolithic thermal bubble printhead

More information (http://inst.eecs.berkeley.edu/~yanw/) or

Send mail to the author : (yanw@eecs.berkeley.edu)

Nanotechnologies for Nanoparticles and Wires

Yang-Kyu Choi1 and Ji Zhu
(Professor Jeffrey Bokor)

The fabrication of nanoscale patterns below 10 nm has been a goal of many researchers for potential applications such as sensors, soft X-ray optical device components, electronic circuit elements, or catalysts. Electron beam lithography is the most commonly used technique for nanometer pattern generation. However, the generation of secondary electrons during electron bombardment makes it difficult to achieve sub-10 nm patterning. Electron beam lithography is also a sequential pattern producing technique and is very time-consuming compared to photolithography-based processes that produce the whole pattern at once using a mask. This is also the case for other scanning probe based lithography techniques. In this work two sub-lithographic patterning technologies, spacer lithography and nanosphere lithography, will be studied. Spacer lithography using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer was demonstrated [1,2]. Sacrificial layers (to support the spacers) were initially defined by conventional lithography and plasma etching. Then, another thin CVD layer that would be spacers was deposited and etched back. After removal of sacrificial structures, these spacers were transferred to a substrate with anisotropic plasma etch. Thus, minimum-sized features were defined not by photoresist but by sidewall spacers deposited by CVD. One of the benefits in the spacer lithography is that it doubles the pattern density achievable by lithography. If this spacer lithography is used n times in succession, 2n lines can generated from a single lithographically defined line. With nanoimprint technology, Pt nanowires and Pt nanoparticles can be fabricated by the spacer lithogrpahy for catalysts and nanowires composed of other materials can be used for chemical and biosensors. Nanopshere lithography uses a monolayer of nanobeads, which are coated by a spinning process [3]. Well-ordered nanogaps can be formed by these adjacent nanobeads. Combining the nanosphere lithography with a metal lift-off process, nanosize metal particles can be patterned, which can be used as catalysts for carbon nanotube growth and as an etch stopper to make nanopillars. The packed nanobeads can also be served as an etch stopper to make nanoholes.

Y.-K. Choi, T.-J. King, and C. Hu, "A Spacer Patterning Technology for Nanoscale CMOS," IEEE Trans. Electron Devices, 2002.
Y.-K. Choi, T.-J. King, and C. Hu, "Spacer FinFET: Nanoscale Double-Gate CMOS Technology for the Terabit Era," Solid-State Electronics, Vol. 46, 2002.
J. C. Hulteen, D. A. Treichel, M. T. Smith, M. L. Duval, T. R. Jensen, and R. P. Van Duyne, "Nanosphere Lithography: Size-Tunable Silver Nanoparticles and Surface Cluster Arrays," J. Physical Chemistry B, Vol. 103, 1999.
1Postdoctoral Researcher

Send mail to the author : (ykchoi@eecs.berkeley.edu)